a51712751c
Utilize common API in PPCTargetParser (https://github.com/llvm/llvm-project/pull/97541) to set default CPU with same interfaces for LLC. This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU to ppc64.
42 lines
1.4 KiB
LLVM
42 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
|
|
; RUN: -mtriple=powerpc64le-linux-gnu < %s | FileCheck \
|
|
; RUN: -check-prefix=CHECK-LE %s
|
|
; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
|
|
; RUN: -mcpu=ppc -mtriple=powerpc64-linux-gnu < %s | FileCheck \
|
|
; RUN: -check-prefix=CHECK-BE %s
|
|
|
|
define i8 @_Z1f1c(i24 %x) #0 {
|
|
; CHECK-LE-LABEL: _Z1f1c:
|
|
; CHECK-LE: # %bb.0:
|
|
; CHECK-LE-NEXT: clrlwi r3, r3, 8
|
|
; CHECK-LE-NEXT: mtfprwz f0, r3
|
|
; CHECK-LE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
|
|
; CHECK-LE-NEXT: lfd f1, .LCPI0_0@toc@l(r3)
|
|
; CHECK-LE-NEXT: xscvuxddp f0, f0
|
|
; CHECK-LE-NEXT: xsmuldp f0, f0, f1
|
|
; CHECK-LE-NEXT: xscvdpsxws f0, f0
|
|
; CHECK-LE-NEXT: mffprwz r3, f0
|
|
; CHECK-LE-NEXT: blr
|
|
;
|
|
; CHECK-BE-LABEL: _Z1f1c:
|
|
; CHECK-BE: # %bb.0:
|
|
; CHECK-BE-NEXT: clrldi r3, r3, 40
|
|
; CHECK-BE-NEXT: std r3, -16(r1)
|
|
; CHECK-BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
|
|
; CHECK-BE-NEXT: lfd f0, -16(r1)
|
|
; CHECK-BE-NEXT: lfd f1, .LCPI0_0@toc@l(r3)
|
|
; CHECK-BE-NEXT: fcfid f0, f0
|
|
; CHECK-BE-NEXT: fmul f0, f0, f1
|
|
; CHECK-BE-NEXT: fctiwz f0, f0
|
|
; CHECK-BE-NEXT: stfd f0, -8(r1)
|
|
; CHECK-BE-NEXT: lwz r3, -4(r1)
|
|
; CHECK-BE-NEXT: blr
|
|
%conv1 = uitofp i24 %x to double
|
|
%mul = fmul double 0.1, %conv1
|
|
%r = fptoui double %mul to i8
|
|
ret i8 %r
|
|
}
|
|
|
|
attributes #0 = { "use-soft-float"="false" }
|