eb7d16ea25
mflr is kind of expensive on Power version smaller than 10, so we should schedule the store for the mflr's def away from mflr. In epilogue, the expensive mtlr has no user for its def, so it doesn't matter that the load and the mtlr are back-to-back. Reviewed By: RolandF Differential Revision: https://reviews.llvm.org/D137423
35 lines
1.3 KiB
LLVM
35 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-openbsd < %s | FileCheck %s
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@.str = private constant [32 x i8] c"i = %g, j = %g, k = %g, l = %g\0A\00", align 1
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define void @callee(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i, float %j, float %k, float %l) nounwind {
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; CHECK-LABEL: callee:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: stwu 1, -16(1)
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; CHECK-NEXT: lfs 1, 24(1)
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; CHECK-NEXT: lis 3, .L.str@ha
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; CHECK-NEXT: lfs 2, 28(1)
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; CHECK-NEXT: la 3, .L.str@l(3)
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; CHECK-NEXT: lfs 3, 32(1)
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; CHECK-NEXT: creqv 6, 6, 6
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; CHECK-NEXT: lfs 4, 36(1)
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; CHECK-NEXT: stw 0, 20(1)
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; CHECK-NEXT: bl printf
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; CHECK-NEXT: lwz 0, 20(1)
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; CHECK-NEXT: addi 1, 1, 16
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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entry:
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%conv = fpext float %i to double
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%conv1 = fpext float %j to double
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%conv2 = fpext float %k to double
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%conv3 = fpext float %l to double
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%call = tail call signext i32 (ptr, ...) @printf(ptr nonnull dereferenceable(1) @.str, double %conv, double %conv1, double %conv2, double %conv3)
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ret void
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}
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declare signext i32 @printf(ptr nocapture readonly, ...)
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