65ae09eeb6
rldimi is 64-bit instruction, so the corresponding builtin should not be available in 32-bit mode. Rotate amount should be in range and cases when mask is zero needs special handling. This change also swaps the first and second operands of rldimi/rlwimi to match previous behavior. For masks not ending at bit 63-SH, rotation will be inserted before rldimi.
121 lines
2.7 KiB
LLVM
121 lines
2.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
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define i32 @test1(i32 %a) {
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; CHECK-LABEL: test1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: rlwinm 3, 3, 0, 4, 19
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; CHECK-NEXT: blr
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entry:
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%tmp.1 = and i32 %a, 268431360
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ret i32 %tmp.1
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}
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define i32 @test2(i32 %a) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: rlwinm 3, 3, 24, 24, 31
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; CHECK-NEXT: blr
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entry:
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%tmp.2 = ashr i32 %a, 8
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%tmp.3 = and i32 %tmp.2, 255
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ret i32 %tmp.3
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}
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define i32 @test3(i32 %a) {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: rlwinm 3, 3, 24, 24, 31
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; CHECK-NEXT: blr
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entry:
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%tmp.3 = lshr i32 %a, 8
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%tmp.4 = and i32 %tmp.3, 255
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ret i32 %tmp.4
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}
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define i32 @test4(i32 %a) {
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; CHECK-LABEL: test4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: rlwinm 3, 3, 8, 0, 8
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; CHECK-NEXT: blr
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entry:
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%tmp.2 = shl i32 %a, 8
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%tmp.3 = and i32 %tmp.2, -8388608
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ret i32 %tmp.3
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}
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define i32 @test5(i32 %a) {
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; CHECK-LABEL: test5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: rlwinm 3, 3, 24, 24, 31
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; CHECK-NEXT: blr
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entry:
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%tmp.1 = and i32 %a, 65280
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%tmp.2 = ashr i32 %tmp.1, 8
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ret i32 %tmp.2
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}
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define i32 @test6(i32 %a) {
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; CHECK-LABEL: test6:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: rlwinm 3, 3, 24, 24, 31
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; CHECK-NEXT: blr
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entry:
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%tmp.1 = and i32 %a, 65280
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%tmp.2 = lshr i32 %tmp.1, 8
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ret i32 %tmp.2
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}
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define i32 @test7(i32 %a) {
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; CHECK-LABEL: test7:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: rlwinm 3, 3, 8, 0, 7
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; CHECK-NEXT: blr
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entry:
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%tmp.1 = and i32 %a, 16711680
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%tmp.2 = shl i32 %tmp.1, 8
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ret i32 %tmp.2
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}
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define i32 @test8(i32 %a, i32 %s) {
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; CHECK-LABEL: test8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: rlwnm 3, 3, 4, 23, 31
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; CHECK-NEXT: blr
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entry:
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%r = call i32 @llvm.ppc.rlwnm(i32 %a, i32 %s, i32 511)
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ret i32 %r
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}
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define i32 @test9(i32 %a) {
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; CHECK-LABEL: test9:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: rlwinm 3, 3, 31, 23, 31
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; CHECK-NEXT: blr
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entry:
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%r = call i32 @llvm.ppc.rlwnm(i32 %a, i32 31, i32 511)
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ret i32 %r
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}
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define i32 @test10(i32 %a, i32 %s) {
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; CHECK-LABEL: test10:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: blr
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entry:
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%r = call i32 @llvm.ppc.rlwnm(i32 %a, i32 %s, i32 0)
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ret i32 %r
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}
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define i32 @test11(i32 %a, i32 %s) {
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; CHECK-LABEL: test11:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: rotlw 3, 3, 4
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; CHECK-NEXT: blr
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entry:
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%r = call i32 @llvm.ppc.rlwnm(i32 %a, i32 %s, i32 -1)
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ret i32 %r
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}
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declare i32 @llvm.ppc.rlwnm(i32, i32, i32 immarg)
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