53c37f300d
On PowerPC there are 128 bit VSX registers. These registers are half overlapped with 64 bit floating point registers (FPR). The 64 bit half of the VXS register that does not overlap with the FPR does not overlap with any other register class. The FPR are the only subregisters of the VSX registers but they do not fully cover the 128 bit super register. This leads to incorrect lane masks being created. This patch adds phony registers for the other half of the VSX registers in order to fully cover them and to make sure that the lane masks are not the same for the VSX and the floating point register.
65 lines
3.3 KiB
YAML
65 lines
3.3 KiB
YAML
# RUN: llc -mcpu=pwr10 -enable-subreg-liveness -filetype=null \
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# RUN: -mtriple=powerpc64le-unknown-linux-gnu -run-pass=greedy,virtregrewriter \
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# RUN: -debug-only=regalloc -o - %s 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# Keep track of all of the lanemasks for various subregsiters.
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#
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# CHECK: %3 [80r,80d:0) 0@80r L000000000000000C [80r,80d:0) 0@80r weight:0.000000e+00
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# CHECK: %4 [96r,96d:0) 0@96r L0000000000003000 [96r,96d:0) 0@96r weight:0.000000e+00
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# CHECK: %5 [112r,112d:0) 0@112r L000000000000000C [112r,112d:0) 0@112r weight:0.000000e+00
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# CHECK: %6 [128r,128d:0) 0@128r L0000000000003000 [128r,128d:0) 0@128r weight:0.000000e+00
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# CHECK: %7 [144r,144d:0) 0@144r L0000000000000004 [144r,144d:0) 0@144r weight:0.000000e+00
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# CHECK: %8 [160r,160d:0) 0@160r L0000000000001000 [160r,160d:0) 0@160r weight:0.000000e+00
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# CHECK: %9 [176r,176d:0) 0@176r L0000000000000004 [176r,176d:0) 0@176r weight:0.000000e+00
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# CHECK: %10 [192r,192d:0) 0@192r L0000000000001000 [192r,192d:0) 0@192r weight:0.000000e+00
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# CHECK: %11 [208r,208d:0) 0@208r L0000000000004000 [208r,208d:0) 0@208r weight:0.000000e+00
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# CHECK: %12 [224r,224d:0) 0@224r L0000000000010000 [224r,224d:0) 0@224r weight:0.000000e+00
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# CHECK: %13 [240r,240d:0) 0@240r L000000000000300C [240r,240d:0) 0@240r weight:0.000000e+00
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# CHECK: %14 [256r,256d:0) 0@256r L000000000003C000 [256r,256d:0) 0@256r weight:0.000000e+00
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# CHECK: 0B bb.0
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# CHECK-NEXT: liveins
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# CHECK-NEXT: 16B %0:vsrc = COPY $v2
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# CHECK-NEXT: 32B %float:fprc = COPY %0.sub_64:vsrc
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# CHECK-NEXT: 48B dead undef %pair.sub_vsx0:vsrprc = COPY $v2
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# CHECK-NEXT: 64B undef %15.sub_vsx1:vsrprc = COPY $v3
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# CHECK-NEXT: 80B dead undef %3.sub_vsx0:vsrprc = COPY %0:vsrc
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# CHECK-NEXT: 96B dead undef %4.sub_vsx1:vsrprc = COPY %0:vsrc
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# CHECK-NEXT: 112B dead undef %5.sub_vsx0:accrc = COPY %0:vsrc
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# CHECK-NEXT: 128B dead undef %6.sub_vsx1:accrc = COPY %0:vsrc
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# CHECK-NEXT: 144B dead undef %7.sub_64:vsrprc = COPY %float:fprc
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# CHECK-NEXT: 160B dead undef %8.sub_vsx1_then_sub_64:vsrprc = COPY %float:fprc
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# CHECK-NEXT: 176B dead undef %9.sub_64:accrc = COPY %float:fprc
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# CHECK-NEXT: 192B dead undef %10.sub_vsx1_then_sub_64:accrc = COPY %float:fprc
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# CHECK-NEXT: 208B dead undef %11.sub_pair1_then_sub_64:accrc = COPY %float:fprc
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# CHECK-NEXT: 224B dead undef %12.sub_pair1_then_sub_vsx1_then_sub_64:accrc = COPY %float:fprc
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# CHECK-NEXT: 240B dead undef %13.sub_pair0:accrc = COPY %15:vsrprc
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# CHECK-NEXT: 256B dead undef %14.sub_pair1:accrc = COPY %15:vsrprc
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---
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name: test
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $v2, $v3
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%0:vsrc = COPY $v2
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%float:fprc = COPY %0.sub_64
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undef %pair.sub_vsx0:vsrprc = COPY $v2
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undef %pair.sub_vsx1:vsrprc = COPY $v3
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undef %1.sub_vsx0:vsrprc = COPY %0
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undef %2.sub_vsx1:vsrprc = COPY %0
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undef %3.sub_vsx0:accrc = COPY %0
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undef %4.sub_vsx1:accrc = COPY %0
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undef %5.sub_64:vsrprc = COPY %float
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undef %6.sub_vsx1_then_sub_64:vsrprc = COPY %float
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undef %7.sub_64:accrc = COPY %float
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undef %8.sub_vsx1_then_sub_64:accrc = COPY %float
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undef %9.sub_pair1_then_sub_64:accrc = COPY %float
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undef %10.sub_pair1_then_sub_vsx1_then_sub_64:accrc = COPY %float
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undef %11.sub_pair0:accrc = COPY %pair
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undef %12.sub_pair1:accrc = COPY %pair
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...
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