a51712751c
Utilize common API in PPCTargetParser (https://github.com/llvm/llvm-project/pull/97541) to set default CPU with same interfaces for LLC. This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU to ppc64.
205 lines
6.0 KiB
LLVM
205 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=ppc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK
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; RUN: llc -mcpu=ppc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-64
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; RUN: llc -filetype=obj -mcpu=ppc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -o %t32.o
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; RUN: llvm-objdump -t --symbol-description %t32.o | FileCheck %s --check-prefix=OBJ32
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; RUN: llc -filetype=obj -mcpu=ppc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s -o %t64.o
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; RUN: llvm-objdump -t --symbol-description %t64.o | FileCheck %s --check-prefix=OBJ64
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@a1 = common global i32 0, align 4 #0
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@a2 = global i32 0, align 4 #0
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@a3 = common global i32 0, align 4
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@a4 = global i32 0, align 4
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define void @set(i32 noundef %_a) {
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; CHECK-LABEL: set:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: la 4, a2[TD](2)
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; CHECK-NEXT: lwz 5, L..C0(2) # @a4
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; CHECK-NEXT: stw 3, 0(4)
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; CHECK-NEXT: la 4, a1[TD](2)
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; CHECK-NEXT: stw 3, 0(4)
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; CHECK-NEXT: lwz 4, L..C1(2) # @a3
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; CHECK-NEXT: stw 3, 0(5)
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; CHECK-NEXT: stw 3, 0(4)
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; CHECK-NEXT: blr
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;
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; CHECK-64-LABEL: set:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: la 4, a2[TD](2)
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; CHECK-64-NEXT: ld 5, L..C0(2) # @a4
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; CHECK-64-NEXT: stw 3, 0(4)
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; CHECK-64-NEXT: la 4, a1[TD](2)
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; CHECK-64-NEXT: stw 3, 0(4)
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; CHECK-64-NEXT: ld 4, L..C1(2) # @a3
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; CHECK-64-NEXT: stw 3, 0(5)
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; CHECK-64-NEXT: stw 3, 0(4)
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; CHECK-64-NEXT: blr
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entry:
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store i32 %_a, ptr @a2, align 4
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store i32 %_a, ptr @a1, align 4
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store i32 %_a, ptr @a4, align 4
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store i32 %_a, ptr @a3, align 4
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ret void
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}
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define i32 @get1() {
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; CHECK-LABEL: get1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: la 3, a2[TD](2)
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; CHECK-NEXT: lwz 3, 0(3)
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; CHECK-NEXT: blr
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;
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; CHECK-64-LABEL: get1:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: la 3, a2[TD](2)
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; CHECK-64-NEXT: lwz 3, 0(3)
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; CHECK-64-NEXT: blr
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entry:
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%0 = load i32, ptr @a2, align 4
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ret i32 %0
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}
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define i32 @get2() {
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; CHECK-LABEL: get2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: la 3, a1[TD](2)
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; CHECK-NEXT: lwz 3, 0(3)
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; CHECK-NEXT: blr
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;
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; CHECK-64-LABEL: get2:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: la 3, a1[TD](2)
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; CHECK-64-NEXT: lwz 3, 0(3)
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; CHECK-64-NEXT: blr
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entry:
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%0 = load i32, ptr @a1, align 4
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ret i32 %0
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}
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define i32 @get3() {
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; CHECK-LABEL: get3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lwz 3, L..C0(2) # @a4
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; CHECK-NEXT: lwz 3, 0(3)
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; CHECK-NEXT: blr
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;
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; CHECK-64-LABEL: get3:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: ld 3, L..C0(2) # @a4
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; CHECK-64-NEXT: lwz 3, 0(3)
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; CHECK-64-NEXT: blr
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entry:
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%0 = load i32, ptr @a4, align 4
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ret i32 %0
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}
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define i32 @get4() {
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; CHECK-LABEL: get4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lwz 3, L..C1(2) # @a3
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; CHECK-NEXT: lwz 3, 0(3)
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; CHECK-NEXT: blr
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;
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; CHECK-64-LABEL: get4:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: ld 3, L..C1(2) # @a3
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; CHECK-64-NEXT: lwz 3, 0(3)
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; CHECK-64-NEXT: blr
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entry:
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%0 = load i32, ptr @a3, align 4
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ret i32 %0
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}
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define nonnull ptr @escape1() {
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; CHECK-LABEL: escape1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: la 3, a2[TD](2)
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; CHECK-NEXT: blr
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;
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; CHECK-64-LABEL: escape1:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: la 3, a2[TD](2)
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; CHECK-64-NEXT: blr
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entry:
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ret ptr @a2
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}
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define nonnull ptr @escape2() {
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; CHECK-LABEL: escape2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: la 3, a1[TD](2)
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; CHECK-NEXT: blr
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;
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; CHECK-64-LABEL: escape2:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: la 3, a1[TD](2)
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; CHECK-64-NEXT: blr
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entry:
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ret ptr @a1
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}
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define nonnull ptr @escape3() {
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; CHECK-LABEL: escape3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lwz 3, L..C0(2) # @a4
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; CHECK-NEXT: blr
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;
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; CHECK-64-LABEL: escape3:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: ld 3, L..C0(2) # @a4
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; CHECK-64-NEXT: blr
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entry:
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ret ptr @a4
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}
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define nonnull ptr @escape4() {
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; CHECK-LABEL: escape4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lwz 3, L..C1(2) # @a3
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; CHECK-NEXT: blr
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;
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; CHECK-64-LABEL: escape4:
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; CHECK-64: # %bb.0: # %entry
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; CHECK-64-NEXT: ld 3, L..C1(2) # @a3
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; CHECK-64-NEXT: blr
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entry:
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ret ptr @a3
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}
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attributes #0 = { "toc-data" }
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; CHECK: .comm a3[RW],4,2 # @a3
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; CHECK-NEXT: .csect a4[RW],2
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; CHECK-NEXT: .globl a4[RW] # @a4
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; CHECK-NEXT: .align 2
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; CHECK-NEXT: .vbyte 4, 0 # 0x0
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; CHECK-NEXT: .toc
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; CHECK-LABEL: L..C0:
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; CHECK-NEXT: .tc a4[TC],a4[RW]
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; CHECK-LABEL: L..C1:
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; CHECK-NEXT: .tc a3[TC],a3[RW]
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; CHECK-NEXT: .csect a2[TD],2
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; CHECK-NEXT: .globl a2[TD] # @a2
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; CHECK-NEXT: .align 2
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; CHECK-NEXT: .vbyte 4, 0 # 0x0
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; CHECK-NEXT: .comm a1[TD],4,2 # @a1
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; OBJ32: {{([[:xdigit:]]{8})}} g O .data 00000004 (idx: {{[0-9]+}}) a4[RW]
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; OBJ32-LABEL: {{([[:xdigit:]]{8})}} l .data 00000000 (idx: {{[0-9]+}}) TOC[TC0]
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; OBJ32-NEXT: {{([[:xdigit:]]{8})}} l O .data 00000004 (idx: {{[0-9]+}}) a4[TC]
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; OBJ32-NEXT: {{([[:xdigit:]]{8})}} l O .data 00000004 (idx: {{[0-9]+}}) a3[TC]
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; OBJ32-NEXT: {{([[:xdigit:]]{8})}} g O .data 00000004 (idx: {{[0-9]+}}) a2[TD]
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; OBJ32-NEXT: {{([[:xdigit:]]{8})}} g O *COM* 00000004 (idx: {{[0-9]+}}) a1[TD]
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; OBJ32-NEXT: {{([[:xdigit:]]{8})}} g O *COM* 00000004 (idx: {{[0-9]+}}) a3[RW]
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; OBJ64: {{([[:xdigit:]]{16})}} g O .data 0000000000000004 (idx: {{[0-9]+}}) a4[RW]
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; OBJ64-LABEL: {{([[:xdigit:]]{16})}} l .data 0000000000000000 (idx: {{[0-9]+}}) TOC[TC0]
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; OBJ64-NEXT: {{([[:xdigit:]]{16})}} l O .data 0000000000000008 (idx: {{[0-9]+}}) a4[TC]
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; OBJ64-NEXT: {{([[:xdigit:]]{16})}} l O .data 0000000000000008 (idx: {{[0-9]+}}) a3[TC]
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; OBJ64-NEXT: {{([[:xdigit:]]{16})}} g O .data 0000000000000004 (idx: {{[0-9]+}}) a2[TD]
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; OBJ64-NEXT: {{([[:xdigit:]]{16})}} g O *COM* 0000000000000004 (idx: {{[0-9]+}}) a1[TD]
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; OBJ64-NEXT: {{([[:xdigit:]]{16})}} g O *COM* 0000000000000004 (idx: {{[0-9]+}}) a3[RW]
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