5d6218d311
For pwr9, xxspltib is a byte splat with a range -128 to 127 - it can be used with a following vector extend sign to make splats of i16, i32, or i64 element size. For pwr8, vspltisw with a following vector extend sign can be used to make splats of i64 elements in the range -16 to 15. Add check for P8 to make sure the 64-bit vector ops are there.
174 lines
5.6 KiB
LLVM
174 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-P9
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-P9
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -mattr=-altivec < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-P9-NOALTIVEC
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-P8
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define <4 x i32> @test_vextsh2w(<4 x i32> %m) {
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; CHECK-P9-LABEL: test_vextsh2w:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: vextsh2w 2, 2
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P9-NOALTIVEC-LABEL: test_vextsh2w:
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; CHECK-P9-NOALTIVEC: # %bb.0: # %entry
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; CHECK-P9-NOALTIVEC-NEXT: extsh 6, 6
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; CHECK-P9-NOALTIVEC-NEXT: extsh 5, 5
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; CHECK-P9-NOALTIVEC-NEXT: extsh 4, 4
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; CHECK-P9-NOALTIVEC-NEXT: extsh 3, 3
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; CHECK-P9-NOALTIVEC-NEXT: blr
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;
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; CHECK-P8-LABEL: test_vextsh2w:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: vspltisw 3, 8
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; CHECK-P8-NEXT: vadduwm 3, 3, 3
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; CHECK-P8-NEXT: vslw 2, 2, 3
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; CHECK-P8-NEXT: vsraw 2, 2, 3
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; CHECK-P8-NEXT: blr
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entry:
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%shl = shl <4 x i32> %m, <i32 16, i32 16, i32 16, i32 16>
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%shr = ashr exact <4 x i32> %shl, <i32 16, i32 16, i32 16, i32 16>
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ret <4 x i32> %shr
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}
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define <4 x i32> @test_vextsb2w(<4 x i32> %m) {
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; CHECK-P9-LABEL: test_vextsb2w:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: vextsb2w 2, 2
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P9-NOALTIVEC-LABEL: test_vextsb2w:
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; CHECK-P9-NOALTIVEC: # %bb.0: # %entry
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; CHECK-P9-NOALTIVEC-NEXT: extsb 6, 6
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; CHECK-P9-NOALTIVEC-NEXT: extsb 5, 5
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; CHECK-P9-NOALTIVEC-NEXT: extsb 4, 4
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; CHECK-P9-NOALTIVEC-NEXT: extsb 3, 3
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; CHECK-P9-NOALTIVEC-NEXT: blr
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;
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; CHECK-P8-LABEL: test_vextsb2w:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: vspltisw 3, 12
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; CHECK-P8-NEXT: vadduwm 3, 3, 3
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; CHECK-P8-NEXT: vslw 2, 2, 3
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; CHECK-P8-NEXT: vsraw 2, 2, 3
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; CHECK-P8-NEXT: blr
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entry:
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%shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24>
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%shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
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ret <4 x i32> %shr
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}
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define <2 x i64> @test_vextsb2d(<2 x i64> %m) {
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; CHECK-P9-LABEL: test_vextsb2d:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: vextsb2d 2, 2
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P9-NOALTIVEC-LABEL: test_vextsb2d:
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; CHECK-P9-NOALTIVEC: # %bb.0: # %entry
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; CHECK-P9-NOALTIVEC-NEXT: extsb 3, 3
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; CHECK-P9-NOALTIVEC-NEXT: extsb 4, 4
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; CHECK-P9-NOALTIVEC-NEXT: blr
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;
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; CHECK-P8-LABEL: test_vextsb2d:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: addis 3, 2, .LCPI2_0@toc@ha
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; CHECK-P8-NEXT: addi 3, 3, .LCPI2_0@toc@l
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; CHECK-P8-NEXT: lxvd2x 35, 0, 3
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; CHECK-P8-NEXT: vsld 2, 2, 3
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; CHECK-P8-NEXT: vsrad 2, 2, 3
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; CHECK-P8-NEXT: blr
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entry:
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%shl = shl <2 x i64> %m, <i64 56, i64 56>
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%shr = ashr exact <2 x i64> %shl, <i64 56, i64 56>
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ret <2 x i64> %shr
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}
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define <2 x i64> @test_vextsh2d(<2 x i64> %m) {
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; CHECK-P9-LABEL: test_vextsh2d:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: vextsh2d 2, 2
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P9-NOALTIVEC-LABEL: test_vextsh2d:
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; CHECK-P9-NOALTIVEC: # %bb.0: # %entry
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; CHECK-P9-NOALTIVEC-NEXT: extsh 3, 3
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; CHECK-P9-NOALTIVEC-NEXT: extsh 4, 4
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; CHECK-P9-NOALTIVEC-NEXT: blr
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;
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; CHECK-P8-LABEL: test_vextsh2d:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: addis 3, 2, .LCPI3_0@toc@ha
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; CHECK-P8-NEXT: addi 3, 3, .LCPI3_0@toc@l
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; CHECK-P8-NEXT: lxvd2x 35, 0, 3
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; CHECK-P8-NEXT: vsld 2, 2, 3
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; CHECK-P8-NEXT: vsrad 2, 2, 3
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; CHECK-P8-NEXT: blr
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entry:
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%shl = shl <2 x i64> %m, <i64 48, i64 48>
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%shr = ashr exact <2 x i64> %shl, <i64 48, i64 48>
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ret <2 x i64> %shr
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}
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define <2 x i64> @test_vextsw2d(<2 x i64> %m) {
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; CHECK-P9-LABEL: test_vextsw2d:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: vextsw2d 2, 2
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P9-NOALTIVEC-LABEL: test_vextsw2d:
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; CHECK-P9-NOALTIVEC: # %bb.0: # %entry
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; CHECK-P9-NOALTIVEC-NEXT: extsw 3, 3
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; CHECK-P9-NOALTIVEC-NEXT: extsw 4, 4
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; CHECK-P9-NOALTIVEC-NEXT: blr
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;
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; CHECK-P8-LABEL: test_vextsw2d:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: addis 3, 2, .LCPI4_0@toc@ha
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; CHECK-P8-NEXT: addi 3, 3, .LCPI4_0@toc@l
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; CHECK-P8-NEXT: lxvd2x 35, 0, 3
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; CHECK-P8-NEXT: vsld 2, 2, 3
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; CHECK-P8-NEXT: vsrad 2, 2, 3
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; CHECK-P8-NEXT: blr
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entry:
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%shl = shl <2 x i64> %m, <i64 32, i64 32>
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%shr = ashr exact <2 x i64> %shl, <i64 32, i64 32>
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ret <2 x i64> %shr
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}
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define <2 x i64> @test_none(<2 x i64> %m) {
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; CHECK-P9-LABEL: test_none:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9-NEXT: xxspltib 35, 16
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; CHECK-P9-NEXT: vextsb2d 3, 3
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; CHECK-P9-NEXT: vsld 2, 2, 3
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; CHECK-P9-NEXT: vsrad 2, 2, 3
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; CHECK-P9-NEXT: blr
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;
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; CHECK-P9-NOALTIVEC-LABEL: test_none:
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; CHECK-P9-NOALTIVEC: # %bb.0: # %entry
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; CHECK-P9-NOALTIVEC-NEXT: sldi 3, 3, 16
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; CHECK-P9-NOALTIVEC-NEXT: sldi 4, 4, 16
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; CHECK-P9-NOALTIVEC-NEXT: sradi 3, 3, 16
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; CHECK-P9-NOALTIVEC-NEXT: sradi 4, 4, 16
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; CHECK-P9-NOALTIVEC-NEXT: blr
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;
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; CHECK-P8-LABEL: test_none:
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; CHECK-P8: # %bb.0: # %entry
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; CHECK-P8-NEXT: addis 3, 2, .LCPI5_0@toc@ha
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; CHECK-P8-NEXT: addi 3, 3, .LCPI5_0@toc@l
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; CHECK-P8-NEXT: lxvd2x 35, 0, 3
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; CHECK-P8-NEXT: vsld 2, 2, 3
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; CHECK-P8-NEXT: vsrad 2, 2, 3
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; CHECK-P8-NEXT: blr
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entry:
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%shl = shl <2 x i64> %m, <i64 16, i64 16>
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%shr = ashr exact <2 x i64> %shl, <i64 16, i64 16>
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ret <2 x i64> %shr
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}
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