49921d1c3c
The xxeval instruction was intorduced in Power PC in Power 10. The instruction accepts three vector registers and an immediate. Depending on the value of the immediate the instruction can be used to perform certain bitwise boolean operations (and, or, xor, ...) on the given vector registers. This patch implements the AND and NAND patterns that can be used by the instruction. Reviewed By: nemanjai, #powerpc, bsaleil, NeHuang, jsji Differential Revision: https://reviews.llvm.org/D92420
190 lines
5.6 KiB
LLVM
190 lines
5.6 KiB
LLVM
; RUN: llc -verify-machineinstrs -mcpu=pwr10 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
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; Function Attrs: nounwind
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; CHECK-LABEL: and_not
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; CHECK: xxlandc v2, v2, v3
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @and_not(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%neg = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1>
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%and = and <4 x i32> %neg, %A
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ret <4 x i32> %and
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: and_and8
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; CHECK: xxeval v2, v3, v2, v4, 1
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; CHECK-NEXT: blr
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define dso_local <16 x i8> @and_and8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) local_unnamed_addr #0 {
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entry:
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%and = and <16 x i8> %B, %A
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%and1 = and <16 x i8> %and, %C
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ret <16 x i8> %and1
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: and_and16
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; CHECK: xxeval v2, v3, v2, v4, 1
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; CHECK-NEXT: blr
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define dso_local <8 x i16> @and_and16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) local_unnamed_addr #0 {
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entry:
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%and = and <8 x i16> %B, %A
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%and1 = and <8 x i16> %and, %C
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ret <8 x i16> %and1
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: and_and32
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; CHECK: xxeval v2, v3, v2, v4, 1
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @and_and32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%and = and <4 x i32> %B, %A
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%and1 = and <4 x i32> %and, %C
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ret <4 x i32> %and1
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: and_and64
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; CHECK: xxeval v2, v3, v2, v4, 1
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; CHECK-NEXT: blr
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define dso_local <2 x i64> @and_and64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C) local_unnamed_addr #0 {
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entry:
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%and = and <2 x i64> %B, %A
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%and1 = and <2 x i64> %and, %C
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ret <2 x i64> %and1
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: and_nand
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; CHECK: xxeval v2, v2, v4, v3, 14
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @and_nand(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%and = and <4 x i32> %C, %B
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%neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>
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%and1 = and <4 x i32> %neg, %A
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ret <4 x i32> %and1
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: and_or
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; CHECK: xxeval v2, v2, v4, v3, 7
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @and_or(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%or = or <4 x i32> %C, %B
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%and = and <4 x i32> %or, %A
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ret <4 x i32> %and
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: and_nor
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; CHECK: xxeval v2, v2, v4, v3, 8
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @and_nor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%or = or <4 x i32> %C, %B
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%neg = xor <4 x i32> %or, <i32 -1, i32 -1, i32 -1, i32 -1>
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%and = and <4 x i32> %neg, %A
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ret <4 x i32> %and
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: and_xor
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; CHECK: xxeval v2, v2, v4, v3, 6
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @and_xor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%xor = xor <4 x i32> %C, %B
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%and = and <4 x i32> %xor, %A
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ret <4 x i32> %and
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: and_eqv
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; CHECK: xxeval v2, v2, v3, v4, 9
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @and_eqv(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%xor = xor <4 x i32> %B, <i32 -1, i32 -1, i32 -1, i32 -1>
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%neg = xor <4 x i32> %xor, %C
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%and = and <4 x i32> %neg, %A
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ret <4 x i32> %and
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: nand_nand
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; CHECK: xxeval v2, v2, v4, v3, 241
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @nand_nand(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%and = and <4 x i32> %C, %B
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%A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
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%neg2 = or <4 x i32> %and, %A.not
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ret <4 x i32> %neg2
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: nand_and
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; CHECK: xxeval v2, v3, v2, v4, 254
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @nand_and(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%and = and <4 x i32> %B, %A
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%and1 = and <4 x i32> %and, %C
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%neg = xor <4 x i32> %and1, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %neg
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: nand_xor
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; CHECK: xxeval v2, v2, v4, v3, 249
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @nand_xor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%xor = xor <4 x i32> %C, %B
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%and = and <4 x i32> %xor, %A
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%neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %neg
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: nand_eqv
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; CHECK: xxeval v2, v2, v4, v3, 246
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @nand_eqv(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%xor = xor <4 x i32> %C, %B
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%A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
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%neg1 = or <4 x i32> %xor, %A.not
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ret <4 x i32> %neg1
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: nand_or
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; CHECK: xxeval v2, v2, v4, v3, 248
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @nand_or(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%or = or <4 x i32> %C, %B
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%and = and <4 x i32> %or, %A
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%neg = xor <4 x i32> %and, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %neg
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}
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; Function Attrs: nounwind
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; CHECK-LABEL: nand_nor
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; CHECK: xxeval v2, v2, v3, v4, 247
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; CHECK-NEXT: blr
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define dso_local <4 x i32> @nand_nor(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) local_unnamed_addr #0 {
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entry:
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%A.not = xor <4 x i32> %A, <i32 -1, i32 -1, i32 -1, i32 -1>
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%or = or <4 x i32> %A.not, %B
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%neg1 = or <4 x i32> %or, %C
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ret <4 x i32> %neg1
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}
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attributes #0 = { nounwind }
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