e5ad7f4556
The `RISCVIndirectBranchTracking` pass inserts `lpad` instruction and could change the basic block alignment, so this should not happen after the branch relaxation as the adjusted offset is possible to exceed the branch range.
221 lines
11 KiB
LLVM
221 lines
11 KiB
LLVM
; RUN: llc -mtriple=riscv32 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
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; RUN: grep -v "Verify generated machine code" | \
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; RUN: FileCheck %s --check-prefixes=CHECK
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; RUN: llc -mtriple=riscv64 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
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; RUN: grep -v "Verify generated machine code" | \
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; RUN: FileCheck %s --check-prefixes=CHECK,RV64
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; REQUIRES: asserts
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; CHECK-LABEL: Pass Arguments:
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; CHECK-NEXT: Target Library Information
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; CHECK-NEXT: Target Pass Configuration
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; CHECK-NEXT: Machine Module Information
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; CHECK-NEXT: Target Transform Information
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; CHECK-NEXT: Assumption Cache Tracker
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; CHECK-NEXT: Profile summary info
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; CHECK-NEXT: Type-Based Alias Analysis
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; CHECK-NEXT: Scoped NoAlias Alias Analysis
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; CHECK-NEXT: Create Garbage Collector Module Metadata
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; CHECK-NEXT: Machine Branch Probability Analysis
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; CHECK-NEXT: Default Regalloc Eviction Advisor
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; CHECK-NEXT: Default Regalloc Priority Advisor
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; CHECK-NEXT: ModulePass Manager
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; CHECK-NEXT: Pre-ISel Intrinsic Lowering
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: Expand large div/rem
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; CHECK-NEXT: Expand fp
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; CHECK-NEXT: Expand Atomic instructions
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; CHECK-NEXT: RISC-V Zacas ABI fix
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Canonicalize natural loops
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; CHECK-NEXT: Lazy Branch Probability Analysis
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; CHECK-NEXT: Lazy Block Frequency Analysis
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; CHECK-NEXT: Optimization Remark Emitter
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; CHECK-NEXT: Scalar Evolution Analysis
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; CHECK-NEXT: Loop Data Prefetch
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; CHECK-NEXT: RISC-V gather/scatter lowering
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; CHECK-NEXT: Interleaved Access Pass
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; CHECK-NEXT: RISC-V CodeGenPrepare
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; CHECK-NEXT: Module Verifier
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Canonicalize natural loops
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; CHECK-NEXT: Scalar Evolution Analysis
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; CHECK-NEXT: Loop Pass Manager
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; CHECK-NEXT: Canonicalize Freeze Instructions in Loops
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; CHECK-NEXT: Induction Variable Users
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; CHECK-NEXT: Loop Strength Reduction
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; CHECK-NEXT: Loop Terminator Folding
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Function Alias Analysis Results
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; CHECK-NEXT: Merge contiguous icmps into a memcmp
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Lazy Branch Probability Analysis
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; CHECK-NEXT: Lazy Block Frequency Analysis
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; CHECK-NEXT: Expand memcmp() to load/stores
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; CHECK-NEXT: Lower Garbage Collection Instructions
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; CHECK-NEXT: Shadow Stack GC Lowering
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; CHECK-NEXT: Remove unreachable blocks from the CFG
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Post-Dominator Tree Construction
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; CHECK-NEXT: Branch Probability Analysis
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; CHECK-NEXT: Block Frequency Analysis
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; CHECK-NEXT: Constant Hoisting
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; CHECK-NEXT: Replace intrinsics with calls to vector library
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; CHECK-NEXT: Lazy Branch Probability Analysis
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; CHECK-NEXT: Lazy Block Frequency Analysis
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; CHECK-NEXT: Optimization Remark Emitter
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; CHECK-NEXT: Partially inline calls to library functions
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; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining)
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; CHECK-NEXT: Scalarize Masked Memory Intrinsics
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; CHECK-NEXT: Expand reduction intrinsics
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Type Promotion
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; CHECK-NEXT: CodeGen Prepare
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Exception handling preparation
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; CHECK-NEXT: A No-Op Barrier Pass
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: Merge internal globals
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; CHECK-NEXT: Dominator Tree Construction
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Function Alias Analysis Results
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; CHECK-NEXT: ObjC ARC contraction
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; CHECK-NEXT: Prepare callbr
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; CHECK-NEXT: Safe Stack instrumentation pass
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; CHECK-NEXT: Insert stack protectors
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; CHECK-NEXT: Module Verifier
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; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
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; CHECK-NEXT: Function Alias Analysis Results
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; CHECK-NEXT: Natural Loop Information
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; CHECK-NEXT: Post-Dominator Tree Construction
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; CHECK-NEXT: Branch Probability Analysis
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; CHECK-NEXT: Assignment Tracking Analysis
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; CHECK-NEXT: Lazy Branch Probability Analysis
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; CHECK-NEXT: Lazy Block Frequency Analysis
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; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection
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; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
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; CHECK-NEXT: RISC-V Vector Peephole Optimization
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; CHECK-NEXT: RISC-V Fold Memory Offset
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Early Tail Duplication
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; CHECK-NEXT: Optimize machine instruction PHIs
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; CHECK-NEXT: Slot index numbering
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; CHECK-NEXT: Merge disjoint stack slots
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; CHECK-NEXT: Local Stack Slot Allocation
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; CHECK-NEXT: Remove dead machine instructions
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: Early Machine Loop Invariant Code Motion
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Common Subexpression Elimination
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Machine Cycle Info Analysis
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; CHECK-NEXT: Machine code sinking
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; CHECK-NEXT: Peephole Optimizations
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; CHECK-NEXT: Remove dead machine instructions
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; CHECK-NEXT: Machine Trace Metrics
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine InstCombiner
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; RV64-NEXT: RISC-V Optimize W Instructions
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; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
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; CHECK-NEXT: RISC-V Merge Base Offset
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: RISC-V VL Optimizer
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; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
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; CHECK-NEXT: RISC-V Insert Write VXRM Pass
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; CHECK-NEXT: RISC-V Landing Pad Setup
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; CHECK-NEXT: RISC-V VMV0 Elimination
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; CHECK-NEXT: Detect Dead Lanes
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; CHECK-NEXT: Init Undef Pass
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; CHECK-NEXT: Process Implicit Definitions
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; CHECK-NEXT: Remove unreachable machine basic blocks
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; CHECK-NEXT: Live Variable Analysis
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; CHECK-NEXT: Eliminate PHI nodes for register allocation
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; CHECK-NEXT: Two-Address instruction pass
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; CHECK-NEXT: Slot index numbering
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; CHECK-NEXT: Live Interval Analysis
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; CHECK-NEXT: Register Coalescer
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; CHECK-NEXT: Rename Disconnected Subregister Components
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; CHECK-NEXT: Machine Instruction Scheduler
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: Debug Variable Analysis
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; CHECK-NEXT: Live Stack Slot Analysis
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; CHECK-NEXT: Virtual Register Map
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; CHECK-NEXT: Live Register Matrix
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; CHECK-NEXT: Bundle Machine CFG Edges
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; CHECK-NEXT: Spill Code Placement Analysis
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: Greedy Register Allocator
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; CHECK-NEXT: Virtual Register Rewriter
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; CHECK-NEXT: RISC-V Insert VSETVLI pass
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; CHECK-NEXT: RISC-V Dead register definitions
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; CHECK-NEXT: Virtual Register Map
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; CHECK-NEXT: Live Register Matrix
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; CHECK-NEXT: Greedy Register Allocator
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; CHECK-NEXT: Virtual Register Rewriter
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; CHECK-NEXT: Register Allocation Pass Scoring
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; CHECK-NEXT: Stack Slot Coloring
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; CHECK-NEXT: Machine Copy Propagation Pass
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; CHECK-NEXT: Machine Loop Invariant Code Motion
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; CHECK-NEXT: RISC-V Redundant Copy Elimination
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; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
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; CHECK-NEXT: Fixup Statepoint Caller Saved
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; CHECK-NEXT: PostRA Machine Sink
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: Shrink Wrapping analysis
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; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
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; CHECK-NEXT: Machine Late Instructions Cleanup Pass
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; CHECK-NEXT: Control Flow Optimizer
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Tail Duplication
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; CHECK-NEXT: Machine Copy Propagation Pass
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; CHECK-NEXT: Post-RA pseudo instruction expansion pass
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; CHECK-NEXT: RISC-V post-regalloc pseudo instruction expansion pass
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; CHECK-NEXT: Insert KCFI indirect call checks
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; CHECK-NEXT: RISC-V Load / Store Optimizer
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; CHECK-NEXT: MachineDominator Tree Construction
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; CHECK-NEXT: Machine Natural Loop Construction
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; CHECK-NEXT: PostRA Machine Instruction Scheduler
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; CHECK-NEXT: Analyze Machine Code For Garbage Collection
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; CHECK-NEXT: Machine Block Frequency Analysis
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Branch Probability Basic Block Placement
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; CHECK-NEXT: Insert fentry calls
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; CHECK-NEXT: Insert XRay ops
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; CHECK-NEXT: Implement the 'patchable-function' attribute
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; CHECK-NEXT: Machine Copy Propagation Pass
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; CHECK-NEXT: RISC-V Late Branch Optimisation Pass
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; CHECK-NEXT: RISC-V Indirect Branch Tracking
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; CHECK-NEXT: Branch relaxation pass
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; CHECK-NEXT: RISC-V Make Compressible
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; CHECK-NEXT: Contiguously Lay Out Funclets
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; CHECK-NEXT: Remove Loads Into Fake Uses
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; CHECK-NEXT: StackMap Liveness Analysis
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; CHECK-NEXT: Live DEBUG_VALUE analysis
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; CHECK-NEXT: Machine Sanitizer Binary Metadata
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; CHECK-NEXT: Machine Outliner
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; CHECK-NEXT: FunctionPass Manager
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; CHECK-NEXT: Insert CFI remember/restore state instructions
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: Stack Frame Layout Analysis
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; CHECK-NEXT: RISC-V Zcmp move merging pass
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; CHECK-NEXT: RISC-V Zcmp Push/Pop optimization pass
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; CHECK-NEXT: RISC-V pseudo instruction expansion pass
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; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
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; CHECK-NEXT: Unpack machine instruction bundles
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; CHECK-NEXT: Lazy Machine Block Frequency Analysis
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; CHECK-NEXT: Machine Optimization Remark Emitter
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; CHECK-NEXT: RISC-V Assembly Printer
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; CHECK-NEXT: Free MachineFunction
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