da19383ae7
This is a more general form of the recently added isel pattern (seteq (i64 (and GPR:$rs1, 0x8000000000000000)), 0) -> (XORI (i64 (SRLI GPR:$rs1, 63)), 1) We can use a shift right for any AND mask that is a negated power of 2. But for every other constant we need to use seqz instead of xori. I don't think there is a benefit to xori over seqz as neither are compressible. We already do this transform from target independent code when the setcc constant is a non-zero subset of the AND mask that is not a legal icmp immediate. I don't believe any of these patterns comparing MSBs to 0 are canonical according to InstCombine. The canonical form is (X < 4096). I'm curious if these appear during SelectionDAG and if so, how. My goal here was just to remove the special case isel patterns.
67 lines
1.6 KiB
LLVM
67 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv32 | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=CHECK,RV64
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define i1 @test1(i64 %x) {
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; RV32-LABEL: test1:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a2, a1, 2
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; RV32-NEXT: srli a0, a0, 30
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; RV32-NEXT: srai a1, a1, 30
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; RV32-NEXT: or a0, a0, a2
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; RV32-NEXT: xori a0, a0, -2
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; RV32-NEXT: not a1, a1
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; RV32-NEXT: or a0, a0, a1
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; RV32-NEXT: seqz a0, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test1:
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; RV64: # %bb.0:
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; RV64-NEXT: srai a0, a0, 30
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; RV64-NEXT: addi a0, a0, 2
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: ret
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%a = and i64 %x, -1073741824
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%b = icmp eq i64 %a, -2147483648
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ret i1 %b
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}
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define i1 @test2(i32 signext %x) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srli a0, a0, 30
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ret
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%a = and i32 %x, -1073741824
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%b = icmp eq i32 %a, 0
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ret i1 %b
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}
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define i1 @test3(i32 signext %x) {
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; CHECK-LABEL: test3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: srli a0, a0, 29
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%a = and i32 %x, -536870912
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%b = icmp ne i32 %a, 0
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ret i1 %b
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}
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define i1 @test4(i64 %x) {
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; RV32-LABEL: test4:
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; RV32: # %bb.0:
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; RV32-NEXT: srli a1, a1, 14
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; RV32-NEXT: seqz a0, a1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: test4:
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; RV64: # %bb.0:
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; RV64-NEXT: srli a0, a0, 46
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; RV64-NEXT: seqz a0, a0
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; RV64-NEXT: ret
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%a = and i64 %x, -70368744177664
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%b = icmp eq i64 %a, 0
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ret i1 %b
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}
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