576d81baa5
Previously we used memory like we do to move between GPRs and FPR64 with the D extension on RV32. We can instead use REG_SEQUENCE/EXTRACT_SUBREG to inform register allocation how to do the copy without memory.
51 lines
1.7 KiB
LLVM
51 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs \
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; RUN: < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs \
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; RUN: < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -mattr=+zdinx -target-abi ilp32 -verify-machineinstrs \
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; RUN: < %s | FileCheck --check-prefix=CHECKRV32ZDINX %s
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; RUN: llc -mtriple=riscv64 -mattr=+zdinx -target-abi lp64 -verify-machineinstrs \
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; RUN: < %s | FileCheck --check-prefix=CHECKRV64ZDINX %s
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define zeroext i1 @double_is_nan(double %a) nounwind {
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; CHECK-LABEL: double_is_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: feq.d a0, fa0, fa0
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; CHECK-NEXT: xori a0, a0, 1
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; CHECK-NEXT: ret
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;
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; CHECKRV32ZDINX-LABEL: double_is_nan:
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; CHECKRV32ZDINX: # %bb.0:
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; CHECKRV32ZDINX-NEXT: feq.d a0, a0, a0
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; CHECKRV32ZDINX-NEXT: xori a0, a0, 1
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; CHECKRV32ZDINX-NEXT: ret
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;
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; CHECKRV64ZDINX-LABEL: double_is_nan:
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; CHECKRV64ZDINX: # %bb.0:
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; CHECKRV64ZDINX-NEXT: feq.d a0, a0, a0
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; CHECKRV64ZDINX-NEXT: xori a0, a0, 1
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; CHECKRV64ZDINX-NEXT: ret
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%1 = fcmp uno double %a, 0.000000e+00
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ret i1 %1
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}
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define zeroext i1 @double_not_nan(double %a) nounwind {
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; CHECK-LABEL: double_not_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: feq.d a0, fa0, fa0
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; CHECK-NEXT: ret
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;
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; CHECKRV32ZDINX-LABEL: double_not_nan:
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; CHECKRV32ZDINX: # %bb.0:
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; CHECKRV32ZDINX-NEXT: feq.d a0, a0, a0
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; CHECKRV32ZDINX-NEXT: ret
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;
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; CHECKRV64ZDINX-LABEL: double_not_nan:
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; CHECKRV64ZDINX: # %bb.0:
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; CHECKRV64ZDINX-NEXT: feq.d a0, a0, a0
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; CHECKRV64ZDINX-NEXT: ret
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%1 = fcmp ord double %a, 0.000000e+00
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ret i1 %1
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}
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