261d4bbb3b
f32 roundeven pattern was missing from RISCVInstrInfoZfa.td. Tests for roundeven.f32/f16/f64 were missing.
365 lines
10 KiB
LLVM
365 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfh < %s \
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; RUN: | FileCheck %s
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; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfh < %s \
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; RUN: | FileCheck %s
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; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfa,+zfhmin < %s \
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; RUN: | FileCheck %s --check-prefix=ZFHMIN
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; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfa,+zfhmin < %s \
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; RUN: | FileCheck %s --check-prefix=ZFHMIN
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declare half @llvm.minimum.f16(half, half)
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define half @fminm_h(half %a, half %b) nounwind {
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; CHECK-LABEL: fminm_h:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fminm.h fa0, fa0, fa1
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fminm_h:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa1
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; ZFHMIN-NEXT: fcvt.s.h fa4, fa0
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; ZFHMIN-NEXT: fminm.s fa5, fa4, fa5
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; ZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZFHMIN-NEXT: ret
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%1 = call half @llvm.minimum.f16(half %a, half %b)
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ret half %1
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}
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declare half @llvm.maximum.f16(half, half)
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define half @fmaxm_h(half %a, half %b) nounwind {
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; CHECK-LABEL: fmaxm_h:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fmaxm.h fa0, fa0, fa1
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fmaxm_h:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa1
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; ZFHMIN-NEXT: fcvt.s.h fa4, fa0
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; ZFHMIN-NEXT: fmaxm.s fa5, fa4, fa5
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; ZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZFHMIN-NEXT: ret
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%1 = tail call half @llvm.maximum.f16(half %a, half %b)
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ret half %1
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}
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define half @fround_h_1(half %a) nounwind {
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; CHECK-LABEL: fround_h_1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fround.h fa0, fa0, rmm
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fround_h_1:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZFHMIN-NEXT: fround.s fa5, fa5, rmm
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; ZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZFHMIN-NEXT: ret
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%call = tail call half @llvm.round.f16(half %a) nounwind readnone
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ret half %call
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}
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declare half @llvm.round.f16(half) nounwind readnone
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define half @fround_h_2(half %a) nounwind {
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; CHECK-LABEL: fround_h_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fround.h fa0, fa0, rdn
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fround_h_2:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZFHMIN-NEXT: fround.s fa5, fa5, rdn
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; ZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZFHMIN-NEXT: ret
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%call = tail call half @llvm.floor.f16(half %a) nounwind readnone
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ret half %call
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}
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declare half @llvm.floor.f16(half) nounwind readnone
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define half @fround_h_3(half %a) nounwind {
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; CHECK-LABEL: fround_h_3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fround.h fa0, fa0, rup
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fround_h_3:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZFHMIN-NEXT: fround.s fa5, fa5, rup
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; ZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZFHMIN-NEXT: ret
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%call = tail call half @llvm.ceil.f16(half %a) nounwind readnone
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ret half %call
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}
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declare half @llvm.ceil.f16(half) nounwind readnone
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define half @fround_h_4(half %a) nounwind {
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; CHECK-LABEL: fround_h_4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fround.h fa0, fa0, rtz
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fround_h_4:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZFHMIN-NEXT: fround.s fa5, fa5, rtz
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; ZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZFHMIN-NEXT: ret
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%call = tail call half @llvm.trunc.f16(half %a) nounwind readnone
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ret half %call
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}
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declare half @llvm.trunc.f16(half) nounwind readnone
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define half @fround_h_5(half %a) nounwind {
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; CHECK-LABEL: fround_h_5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fround.h fa0, fa0
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fround_h_5:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZFHMIN-NEXT: fround.s fa5, fa5
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; ZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZFHMIN-NEXT: ret
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%call = tail call half @llvm.nearbyint.f16(half %a) nounwind readnone
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ret half %call
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}
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declare half @llvm.nearbyint.f16(half) nounwind readnone
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define half @fround_h_6(half %a) nounwind {
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; CHECK-LABEL: fround_h_6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fround.h fa0, fa0, rne
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fround_h_6:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZFHMIN-NEXT: fround.s fa5, fa5, rne
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; ZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZFHMIN-NEXT: ret
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%call = tail call half @llvm.roundeven.f16(half %a) nounwind readnone
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ret half %call
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}
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declare half @llvm.roundeven.f16(half) nounwind readnone
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define half @froundnx_h(half %a) nounwind {
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; CHECK-LABEL: froundnx_h:
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; CHECK: # %bb.0:
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; CHECK-NEXT: froundnx.h fa0, fa0
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: froundnx_h:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZFHMIN-NEXT: froundnx.s fa5, fa5
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; ZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZFHMIN-NEXT: ret
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%call = tail call half @llvm.rint.f16(half %a) nounwind readnone
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ret half %call
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}
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declare half @llvm.rint.f16(half) nounwind readnone
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declare i1 @llvm.experimental.constrained.fcmp.f16(half, half, metadata, metadata)
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define i32 @fcmp_olt_q(half %a, half %b) nounwind strictfp {
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; CHECK-LABEL: fcmp_olt_q:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fltq.h a0, fa0, fa1
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fcmp_olt_q:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa1
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; ZFHMIN-NEXT: fcvt.s.h fa4, fa0
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; ZFHMIN-NEXT: fltq.s a0, fa4, fa5
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; ZFHMIN-NEXT: ret
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%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ole_q(half %a, half %b) nounwind strictfp {
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; CHECK-LABEL: fcmp_ole_q:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fleq.h a0, fa0, fa1
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fcmp_ole_q:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa1
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; ZFHMIN-NEXT: fcvt.s.h fa4, fa0
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; ZFHMIN-NEXT: fleq.s a0, fa4, fa5
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; ZFHMIN-NEXT: ret
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%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_one_q(half %a, half %b) nounwind strictfp {
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; CHECK-LABEL: fcmp_one_q:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fltq.h a0, fa0, fa1
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; CHECK-NEXT: fltq.h a1, fa1, fa0
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; CHECK-NEXT: or a0, a1, a0
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fcmp_one_q:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa1
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; ZFHMIN-NEXT: fcvt.s.h fa4, fa0
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; ZFHMIN-NEXT: fltq.s a0, fa4, fa5
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; ZFHMIN-NEXT: fltq.s a1, fa5, fa4
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; ZFHMIN-NEXT: or a0, a1, a0
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; ZFHMIN-NEXT: ret
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%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"one", metadata !"fpexcept.strict") strictfp
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ueq_q(half %a, half %b) nounwind strictfp {
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; CHECK-LABEL: fcmp_ueq_q:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fltq.h a0, fa0, fa1
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; CHECK-NEXT: fltq.h a1, fa1, fa0
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; CHECK-NEXT: or a0, a1, a0
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; CHECK-NEXT: xori a0, a0, 1
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fcmp_ueq_q:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa1
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; ZFHMIN-NEXT: fcvt.s.h fa4, fa0
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; ZFHMIN-NEXT: fltq.s a0, fa4, fa5
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; ZFHMIN-NEXT: fltq.s a1, fa5, fa4
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; ZFHMIN-NEXT: or a0, a1, a0
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; ZFHMIN-NEXT: xori a0, a0, 1
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; ZFHMIN-NEXT: ret
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%1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define half @fadd_neg_0p5(half %x) {
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; CHECK-LABEL: fadd_neg_0p5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fli.h fa5, 0.5
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; CHECK-NEXT: fsub.h fa0, fa0, fa5
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fadd_neg_0p5:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZFHMIN-NEXT: fli.s fa4, 0.5
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; ZFHMIN-NEXT: fsub.s fa5, fa5, fa4
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; ZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZFHMIN-NEXT: ret
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%a = fadd half %x, -0.5
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ret half %a
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}
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define half @fma_neg_addend(half %x, half %y) nounwind {
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; CHECK-LABEL: fma_neg_addend:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fli.h fa5, 0.5
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; CHECK-NEXT: fmsub.h fa0, fa0, fa1, fa5
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fma_neg_addend:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa1
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; ZFHMIN-NEXT: fcvt.s.h fa4, fa0
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; ZFHMIN-NEXT: fli.s fa3, 0.5
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; ZFHMIN-NEXT: fmsub.s fa5, fa4, fa5, fa3
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; ZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZFHMIN-NEXT: ret
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%a = call half @llvm.fma.f32(half %x, half %y, half -0.5)
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ret half %a
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}
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define half @fma_neg_multiplicand(half %x, half %y) nounwind {
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; CHECK-LABEL: fma_neg_multiplicand:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fli.h fa5, 0.125
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; CHECK-NEXT: fnmsub.h fa0, fa5, fa0, fa1
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fma_neg_multiplicand:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa1
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; ZFHMIN-NEXT: fcvt.s.h fa4, fa0
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; ZFHMIN-NEXT: fli.s fa3, 0.125
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; ZFHMIN-NEXT: fnmsub.s fa5, fa3, fa4, fa5
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; ZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZFHMIN-NEXT: ret
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%a = call half @llvm.fma.f32(half %x, half -0.125, half %y)
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ret half %a
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}
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define half @fma_neg_addend_multiplicand(half %x) nounwind {
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; CHECK-LABEL: fma_neg_addend_multiplicand:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fli.h fa5, 0.25
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; CHECK-NEXT: fli.h fa4, 0.5
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; CHECK-NEXT: fnmadd.h fa0, fa4, fa0, fa5
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: fma_neg_addend_multiplicand:
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; ZFHMIN: # %bb.0:
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZFHMIN-NEXT: fli.s fa4, 0.25
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; ZFHMIN-NEXT: fli.s fa3, 0.5
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; ZFHMIN-NEXT: fnmadd.s fa5, fa3, fa5, fa4
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; ZFHMIN-NEXT: fcvt.h.s fa0, fa5
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; ZFHMIN-NEXT: ret
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%a = call half @llvm.fma.f32(half %x, half -0.5, half -0.25)
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ret half %a
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}
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define half @select_loadfpimm(half %x) nounwind {
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; CHECK-LABEL: select_loadfpimm:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fmv.h.x fa5, zero
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; CHECK-NEXT: fle.h a0, fa5, fa0
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; CHECK-NEXT: fli.h fa0, 0.5
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; CHECK-NEXT: bnez a0, .LBB17_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: fneg.h fa0, fa0
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; CHECK-NEXT: .LBB17_2: # %entry
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; CHECK-NEXT: ret
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;
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; ZFHMIN-LABEL: select_loadfpimm:
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; ZFHMIN: # %bb.0: # %entry
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; ZFHMIN-NEXT: fcvt.s.h fa5, fa0
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; ZFHMIN-NEXT: fmv.w.x fa4, zero
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; ZFHMIN-NEXT: fle.s a0, fa4, fa5
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; ZFHMIN-NEXT: xori a0, a0, 1
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; ZFHMIN-NEXT: slli a0, a0, 1
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; ZFHMIN-NEXT: lui a1, %hi(.LCPI17_0)
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; ZFHMIN-NEXT: addi a1, a1, %lo(.LCPI17_0)
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; ZFHMIN-NEXT: add a0, a1, a0
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; ZFHMIN-NEXT: flh fa0, 0(a0)
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; ZFHMIN-NEXT: ret
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entry:
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%cmp = fcmp ult half %x, 0.000000e+00
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%sel = select i1 %cmp, half -5.000000e-01, half 5.000000e-01
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ret half %sel
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}
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