059722da5e
This reverts commit 9cc8442a2b438962883bbbfd8ff62ad4b1a2b95d. This reverts commit 859c871184bdfdebb47b5c7ec5e59348e0534e0b. A performance regression was reported on the original review. There appears to have been an unexpected interaction here. Reverting during investigation.
373 lines
10 KiB
LLVM
373 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=CHECK,RV32ZBB
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define i32 @orc_b_i32_mul255(i32 %x) nounwind {
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; RV32I-LABEL: orc_b_i32_mul255:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a1, 4112
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; RV32I-NEXT: addi a1, a1, 257
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: slli a1, a0, 8
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; RV32I-NEXT: sub a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: orc_b_i32_mul255:
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; RV32ZBB: # %bb.0: # %entry
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; RV32ZBB-NEXT: lui a1, 4112
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; RV32ZBB-NEXT: addi a1, a1, 257
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; RV32ZBB-NEXT: and a0, a0, a1
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; RV32ZBB-NEXT: orc.b a0, a0
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; RV32ZBB-NEXT: ret
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entry:
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%and = and i32 %x, 16843009
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%mul = mul nuw nsw i32 %and, 255
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ret i32 %mul
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}
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define i32 @orc_b_i32_sub_shl8x_x_lsb(i32 %x) {
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; RV32I-LABEL: orc_b_i32_sub_shl8x_x_lsb:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a1, 4112
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; RV32I-NEXT: addi a1, a1, 257
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: slli a1, a0, 8
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; RV32I-NEXT: sub a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_lsb:
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; RV32ZBB: # %bb.0: # %entry
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; RV32ZBB-NEXT: lui a1, 4112
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; RV32ZBB-NEXT: addi a1, a1, 257
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; RV32ZBB-NEXT: and a0, a0, a1
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; RV32ZBB-NEXT: orc.b a0, a0
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; RV32ZBB-NEXT: ret
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entry:
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%and = and i32 %x, 16843009
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%sub = mul nuw i32 %and, 255
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_shl8x_x_lsb_preshifted(i32 %x){
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; RV32I-LABEL: orc_b_i32_sub_shl8x_x_lsb_preshifted:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: srli a0, a0, 11
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; RV32I-NEXT: lui a1, 16
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; RV32I-NEXT: addi a1, a1, 257
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: slli a1, a0, 8
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; RV32I-NEXT: sub a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_lsb_preshifted:
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; RV32ZBB: # %bb.0: # %entry
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; RV32ZBB-NEXT: srli a0, a0, 11
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; RV32ZBB-NEXT: lui a1, 16
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; RV32ZBB-NEXT: addi a1, a1, 257
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; RV32ZBB-NEXT: and a0, a0, a1
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; RV32ZBB-NEXT: orc.b a0, a0
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; RV32ZBB-NEXT: ret
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entry:
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%shr = lshr i32 %x, 11
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%and = and i32 %shr, 16843009
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%sub = mul nuw i32 %and, 255
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_shl8x_x_b1(i32 %x) {
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; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a1, 8224
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; RV32I-NEXT: addi a1, a1, 514
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: slli a1, a0, 7
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; RV32I-NEXT: srli a0, a0, 1
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; RV32I-NEXT: sub a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1:
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; RV32ZBB: # %bb.0: # %entry
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; RV32ZBB-NEXT: lui a1, 8224
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; RV32ZBB-NEXT: addi a1, a1, 514
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; RV32ZBB-NEXT: and a0, a0, a1
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; RV32ZBB-NEXT: orc.b a0, a0
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; RV32ZBB-NEXT: ret
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entry:
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%and = and i32 %x, 33686018
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%shl = shl i32 %and, 7
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%shr = lshr exact i32 %and, 1
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%sub = sub nsw i32 %shl, %shr
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_shl8x_x_b2(i32 %x) {
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; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b2:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a1, 16448
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; RV32I-NEXT: addi a1, a1, 1028
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: slli a1, a0, 6
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; RV32I-NEXT: srli a0, a0, 2
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; RV32I-NEXT: sub a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b2:
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; RV32ZBB: # %bb.0: # %entry
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; RV32ZBB-NEXT: lui a1, 16448
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; RV32ZBB-NEXT: addi a1, a1, 1028
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; RV32ZBB-NEXT: and a0, a0, a1
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; RV32ZBB-NEXT: orc.b a0, a0
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; RV32ZBB-NEXT: ret
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entry:
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%and = and i32 %x, 67372036
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%shl = shl i32 %and, 6
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%shr = lshr exact i32 %and, 2
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%sub = sub nsw i32 %shl, %shr
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_shl8x_x_b3(i32 %x) {
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; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a1, 24672
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; CHECK-NEXT: addi a1, a1, 1542
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; CHECK-NEXT: and a0, a0, a1
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; CHECK-NEXT: slli a1, a0, 5
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; CHECK-NEXT: srli a0, a0, 3
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; CHECK-NEXT: sub a0, a1, a0
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; CHECK-NEXT: ret
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entry:
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%and = and i32 %x, 101058054
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%shl = shl nuw i32 %and, 5
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%shr = lshr i32 %and, 3
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%sub = sub nsw i32 %shl, %shr
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_shl8x_x_b4(i32 %x) {
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; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a1, 32897
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; CHECK-NEXT: addi a1, a1, -2040
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; CHECK-NEXT: and a0, a0, a1
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; CHECK-NEXT: slli a1, a0, 4
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; CHECK-NEXT: srli a0, a0, 4
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; CHECK-NEXT: sub a0, a1, a0
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; CHECK-NEXT: ret
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entry:
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%and = and i32 %x, 134744072
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%shl = shl nuw i32 %and, 4
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%shr = lshr i32 %and, 4
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%sub = sub nsw i32 %shl, %shr
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_shl8x_x_b5(i32 %x) {
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; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a1, 65793
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; CHECK-NEXT: addi a1, a1, 16
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; CHECK-NEXT: and a0, a0, a1
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; CHECK-NEXT: slli a1, a0, 3
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; CHECK-NEXT: srli a0, a0, 5
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; CHECK-NEXT: sub a0, a1, a0
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; CHECK-NEXT: ret
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entry:
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%and = and i32 %x, 269488144
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%shl = shl nuw i32 %and, 3
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%shr = lshr i32 %and, 5
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%sub = sub nsw i32 %shl, %shr
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_shl8x_x_b6(i32 %x) {
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; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b6:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a1, 131586
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; CHECK-NEXT: addi a1, a1, 32
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; CHECK-NEXT: and a0, a0, a1
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; CHECK-NEXT: slli a1, a0, 2
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; CHECK-NEXT: srli a0, a0, 6
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; CHECK-NEXT: sub a0, a1, a0
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; CHECK-NEXT: ret
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entry:
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%and = and i32 %x, 538976288
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%shl = shl nuw i32 %and, 2
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%shr = lshr i32 %and, 6
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%sub = sub nsw i32 %shl, %shr
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_shl8x_x_b7(i32 %x) {
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; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b7:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a1, 263172
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; CHECK-NEXT: addi a1, a1, 64
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; CHECK-NEXT: and a0, a0, a1
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; CHECK-NEXT: slli a1, a0, 1
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; CHECK-NEXT: srli a0, a0, 7
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; CHECK-NEXT: sub a0, a1, a0
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; CHECK-NEXT: ret
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entry:
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%and = and i32 %x, 1077952576
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%shl = shl nuw i32 %and, 1
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%shr = lshr i32 %and, 7
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%sub = sub nsw i32 %shl, %shr
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_shl8x_x_b1_shl_used(i32 %x, ptr %arr) {
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; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_shl_used:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a2, 8224
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; RV32I-NEXT: addi a2, a2, 514
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: slli a2, a0, 7
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; RV32I-NEXT: srli a3, a0, 1
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; RV32I-NEXT: sub a0, a2, a3
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; RV32I-NEXT: sw a3, 0(a1)
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_shl_used:
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; RV32ZBB: # %bb.0: # %entry
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; RV32ZBB-NEXT: lui a2, 8224
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; RV32ZBB-NEXT: addi a2, a2, 514
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; RV32ZBB-NEXT: and a0, a0, a2
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; RV32ZBB-NEXT: srli a2, a0, 1
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; RV32ZBB-NEXT: orc.b a0, a0
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; RV32ZBB-NEXT: sw a2, 0(a1)
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; RV32ZBB-NEXT: ret
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entry:
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%and = and i32 %x, 33686018
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%shl = shl i32 %and, 7
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%shr = lshr exact i32 %and, 1
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store i32 %shr, ptr %arr, align 4
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%sub = sub nsw i32 %shl, %shr
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_shl8x_x_b1_srl_used(i32 %x, ptr %arr) {
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; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_srl_used:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a2, 8224
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; RV32I-NEXT: addi a2, a2, 514
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: slli a2, a0, 7
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; RV32I-NEXT: srli a0, a0, 1
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; RV32I-NEXT: sub a0, a2, a0
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; RV32I-NEXT: sw a2, 0(a1)
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_srl_used:
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; RV32ZBB: # %bb.0: # %entry
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; RV32ZBB-NEXT: lui a2, 8224
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; RV32ZBB-NEXT: addi a2, a2, 514
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; RV32ZBB-NEXT: and a0, a0, a2
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; RV32ZBB-NEXT: slli a2, a0, 7
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; RV32ZBB-NEXT: orc.b a0, a0
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; RV32ZBB-NEXT: sw a2, 0(a1)
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; RV32ZBB-NEXT: ret
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entry:
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%and = and i32 %x, 33686018
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%shl = shl i32 %and, 7
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%shr = lshr exact i32 %and, 1
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store i32 %shl, ptr %arr, align 4
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%sub = sub nsw i32 %shl, %shr
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_shl8x_x_b1_not_used(i32 %x, ptr %arr) {
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; RV32I-LABEL: orc_b_i32_sub_shl8x_x_b1_not_used:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: lui a1, 8224
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; RV32I-NEXT: addi a1, a1, 514
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: slli a1, a0, 7
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; RV32I-NEXT: srli a0, a0, 1
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; RV32I-NEXT: sub a0, a1, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: orc_b_i32_sub_shl8x_x_b1_not_used:
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; RV32ZBB: # %bb.0: # %entry
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; RV32ZBB-NEXT: lui a1, 8224
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; RV32ZBB-NEXT: addi a1, a1, 514
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; RV32ZBB-NEXT: and a0, a0, a1
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; RV32ZBB-NEXT: orc.b a0, a0
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; RV32ZBB-NEXT: ret
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entry:
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%and = and i32 %x, 33686018
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%shl = shl i32 %and, 7
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%shr = lshr exact i32 %and, 1
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%sub = sub nsw i32 %shl, %shr
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_shl8x_x_shl_used(i32 %x, ptr %arr){
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; CHECK-LABEL: orc_b_i32_sub_shl8x_x_shl_used:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a2, 4112
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; CHECK-NEXT: addi a2, a2, 257
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; CHECK-NEXT: and a0, a0, a2
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; CHECK-NEXT: slli a2, a0, 8
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; CHECK-NEXT: sub a0, a2, a0
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; CHECK-NEXT: sw a2, 0(a1)
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; CHECK-NEXT: ret
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entry:
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%and = and i32 %x, 16843009
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%shl = shl i32 %and, 8
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store i32 %shl, ptr %arr, align 4
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%sub = mul nuw i32 %and, 255
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_shl8x_x_b1_both_used(i32 %x, ptr %arr) {
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; CHECK-LABEL: orc_b_i32_sub_shl8x_x_b1_both_used:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a2, 8224
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; CHECK-NEXT: addi a2, a2, 514
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; CHECK-NEXT: and a0, a0, a2
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; CHECK-NEXT: slli a2, a0, 7
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; CHECK-NEXT: srli a3, a0, 1
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; CHECK-NEXT: sub a0, a2, a3
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; CHECK-NEXT: sw a2, 0(a1)
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; CHECK-NEXT: sw a3, 4(a1)
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; CHECK-NEXT: ret
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entry:
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%and = and i32 %x, 33686018
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%shl = shl i32 %and, 7
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%shr = lshr exact i32 %and, 1
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store i32 %shl, ptr %arr, align 4
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%arrayidx1 = getelementptr inbounds i8, ptr %arr, i32 4
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store i32 %shr, ptr %arrayidx1, align 4
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%sub = sub nsw i32 %shl, %shr
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ret i32 %sub
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}
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define i32 @orc_b_i32_sub_x_shr8x(i32 %x) {
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; CHECK-LABEL: orc_b_i32_sub_x_shr8x:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lui a1, 4112
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; CHECK-NEXT: addi a1, a1, 257
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; CHECK-NEXT: and a0, a0, a1
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; CHECK-NEXT: srli a1, a0, 8
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; CHECK-NEXT: sub a0, a0, a1
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; CHECK-NEXT: ret
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entry:
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%and = and i32 %x, 16843009
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%shr = lshr i32 %and, 8
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%sub = sub nsw i32 %and, %shr
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ret i32 %sub
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}
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