6affe87bda
We try to match as a disguised rotate by constant of these forms (shl (X | Y), C1) | (srl X, C2) --> (rotl X, C1) | (shl Y, C1) (shl X, C1) | (srl (X | Y), C2) --> (rotl X, C1) | (srl Y, C2) We may have also looked through an AND to find the shift. If we did, we need to apply a mask to the result. I'll add an AArch64 test and pre-commit it and the RISC-V test tomorrow. Fixes PR55201. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D124711
18 lines
458 B
LLVM
18 lines
458 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 -mattr=+zbb | FileCheck %s
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define i32 @f(i32 %x) {
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; CHECK-LABEL: f:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rori a0, a0, 27
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; CHECK-NEXT: ori a0, a0, 32
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; CHECK-NEXT: andi a0, a0, -31
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; CHECK-NEXT: ret
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%or1 = or i32 %x, 1
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%sh1 = shl i32 %or1, 5
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%sh2 = lshr i32 %x, 27
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%1 = and i32 %sh2, 1
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%r = or i32 %sh1, %1
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ret i32 %r
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}
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