9fb4bc5bf4
Check to see if we are only demanding (shifted) signbits from a SRL node that are also signbits in the source node. We can't demand any upper zero bits that the SRL will shift in (up to max shift amount), and the lower demanded bits bound must already be all signbits.
37 lines
1.1 KiB
LLVM
37 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s
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; regression due to creation of temporary i32 avgfloors node
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define signext i64 @PR95284(i32 signext %0) {
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; RV32I-LABEL: PR95284:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: addi a1, a0, -1
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; RV32I-NEXT: seqz a0, a0
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; RV32I-NEXT: slli a2, a0, 31
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; RV32I-NEXT: srli a1, a1, 1
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; RV32I-NEXT: or a1, a1, a2
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; RV32I-NEXT: addi a1, a1, 1
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; RV32I-NEXT: seqz a2, a1
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; RV32I-NEXT: sub a2, a2, a0
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; RV32I-NEXT: andi a0, a1, -2
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; RV32I-NEXT: slli a1, a2, 1
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; RV32I-NEXT: srli a1, a1, 1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: PR95284:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: srli a0, a0, 1
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; RV64I-NEXT: addi a0, a0, 1
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; RV64I-NEXT: andi a0, a0, -2
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; RV64I-NEXT: ret
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entry:
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%1 = zext nneg i32 %0 to i64
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%2 = add nsw i64 %1, -1
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%3 = lshr i64 %2, 1
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%4 = add nuw nsw i64 %3, 1
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%5 = and i64 %4, 9223372036854775806
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ret i64 %5
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}
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