
This is largely a revert of commit e81796671890b59c110f8e41adc7ca26f8484d20. As #88029 shows, there exists hardware that only supports unaligned scalar. I'm leaving how this gets exposed to the clang interface to a future patch.
45 lines
1.0 KiB
LLVM
45 lines
1.0 KiB
LLVM
; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -verify-machineinstrs < %s | FileCheck %s
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; CHECK: .option push
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; CHECK-NEXT: .option arch, +v, +zve32f, +zve32x, +zve64d, +zve64f, +zve64x, +zvl128b, +zvl32b, +zvl64b
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define void @test1() "target-features"="+a,+d,+f,+m,+c,+v,+zifencei,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" {
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; CHECK-LABEL: test1
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; CHECK: .option pop
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entry:
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ret void
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}
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; CHECK: .option push
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; CHECK-NEXT: .option arch, +zihintntl
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define void @test2() "target-features"="+a,+d,+f,+m,+zihintntl,+zifencei" {
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; CHECK-LABEL: test2
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; CHECK: .option pop
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entry:
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ret void
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}
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; CHECK: .option push
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; CHECK-NEXT: .option arch, -a, -d, -f, -m
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define void @test3() "target-features"="-a,-d,-f,-m" {
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; CHECK-LABEL: test3
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; CHECK: .option pop
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entry:
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ret void
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}
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; CHECK-NOT: .option push
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define void @test4() {
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; CHECK-LABEL: test4
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; CHECK-NOT: .option pop
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entry:
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ret void
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}
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; CHECK-NOT: .option push
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define void @test5() "target-features"="+unaligned-scalar-mem" {
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; CHECK-LABEL: test5
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; CHECK-NOT: .option pop
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entry:
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ret void
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}
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