059722da5e
This reverts commit 9cc8442a2b438962883bbbfd8ff62ad4b1a2b95d. This reverts commit 859c871184bdfdebb47b5c7ec5e59348e0534e0b. A performance regression was reported on the original review. There appears to have been an unexpected interaction here. Reverting during investigation.
144 lines
4.1 KiB
LLVM
144 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s
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define i64 @test_Pr_wide_scalar_simple(i64 noundef %0) nounwind {
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; CHECK-LABEL: test_Pr_wide_scalar_simple:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: #APP
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; CHECK-NEXT: # a2 <- a0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: mv a1, a3
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; CHECK-NEXT: ret
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entry:
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%1 = call i64 asm sideeffect "/* $0 <- $1 */", "=&R,R"(i64 %0)
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ret i64 %1
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}
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define i32 @test_Pr_wide_scalar_with_ops(i32 noundef %0) nounwind {
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; CHECK-LABEL: test_Pr_wide_scalar_with_ops:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mv a1, a0
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; CHECK-NEXT: #APP
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; CHECK-NEXT: # a2 <- a0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: or a0, a2, a3
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; CHECK-NEXT: ret
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entry:
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%1 = zext i32 %0 to i64
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%2 = shl i64 %1, 32
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%3 = or i64 %1, %2
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%4 = call i64 asm sideeffect "/* $0 <- $1 */", "=&R,R"(i64 %3)
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%5 = trunc i64 %4 to i32
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%6 = lshr i64 %4, 32
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%7 = trunc i64 %6 to i32
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%8 = or i32 %5, %7
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ret i32 %8
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}
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define i64 @test_Pr_wide_scalar_inout(ptr %0, i64 noundef %1) nounwind {
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; CHECK-LABEL: test_Pr_wide_scalar_inout:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: mv a3, a2
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; CHECK-NEXT: sw a0, 12(sp)
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; CHECK-NEXT: mv a2, a1
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; CHECK-NEXT: sw a1, 0(sp)
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; CHECK-NEXT: sw a3, 4(sp)
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; CHECK-NEXT: #APP
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; CHECK-NEXT: # a0; a2
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: sw a0, 12(sp)
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; CHECK-NEXT: sw a2, 0(sp)
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; CHECK-NEXT: sw a3, 4(sp)
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: mv a1, a3
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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entry:
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%2 = alloca ptr, align 4
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%3 = alloca i64, align 8
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store ptr %0, ptr %2, align 4
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store i64 %1, ptr %3, align 8
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%4 = load ptr, ptr %2, align 4
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%5 = load i64, ptr %3, align 8
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%6 = call { ptr, i64 } asm sideeffect "/* $0; $1 */", "=r,=R,0,1"(ptr %4, i64 %5)
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%7 = extractvalue { ptr, i64} %6, 0
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%8 = extractvalue { ptr, i64 } %6, 1
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store ptr %7, ptr %2, align 4
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store i64 %8, ptr %3, align 8
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%9 = load i64, ptr %3, align 8
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ret i64 %9
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}
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define i64 @test_cR_wide_scalar_simple(i64 noundef %0) nounwind {
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; CHECK-LABEL: test_cR_wide_scalar_simple:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: #APP
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; CHECK-NEXT: # a2 <- a0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: mv a1, a3
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; CHECK-NEXT: ret
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entry:
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%1 = call i64 asm sideeffect "/* $0 <- $1 */", "=&^cR,^cR"(i64 %0)
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ret i64 %1
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}
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define i32 @test_cR_wide_scalar_with_ops(i32 noundef %0) nounwind {
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; CHECK-LABEL: test_cR_wide_scalar_with_ops:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mv a1, a0
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; CHECK-NEXT: #APP
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; CHECK-NEXT: # a2 <- a0
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: or a0, a2, a3
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; CHECK-NEXT: ret
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entry:
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%1 = zext i32 %0 to i64
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%2 = shl i64 %1, 32
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%3 = or i64 %1, %2
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%4 = call i64 asm sideeffect "/* $0 <- $1 */", "=&^cR,^cR"(i64 %3)
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%5 = trunc i64 %4 to i32
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%6 = lshr i64 %4, 32
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%7 = trunc i64 %6 to i32
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%8 = or i32 %5, %7
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ret i32 %8
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}
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define i64 @test_cR_wide_scalar_inout(ptr %0, i64 noundef %1) nounwind {
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; CHECK-LABEL: test_cR_wide_scalar_inout:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: mv a3, a2
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; CHECK-NEXT: sw a0, 12(sp)
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; CHECK-NEXT: mv a2, a1
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; CHECK-NEXT: sw a1, 0(sp)
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; CHECK-NEXT: sw a3, 4(sp)
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; CHECK-NEXT: #APP
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; CHECK-NEXT: # a0; a2
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: sw a0, 12(sp)
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; CHECK-NEXT: sw a2, 0(sp)
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; CHECK-NEXT: sw a3, 4(sp)
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; CHECK-NEXT: mv a0, a2
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; CHECK-NEXT: mv a1, a3
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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entry:
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%2 = alloca ptr, align 4
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%3 = alloca i64, align 8
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store ptr %0, ptr %2, align 4
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store i64 %1, ptr %3, align 8
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%4 = load ptr, ptr %2, align 4
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%5 = load i64, ptr %3, align 8
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%6 = call { ptr, i64 } asm sideeffect "/* $0; $1 */", "=r,=^cR,0,1"(ptr %4, i64 %5)
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%7 = extractvalue { ptr, i64} %6, 0
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%8 = extractvalue { ptr, i64 } %6, 1
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store ptr %7, ptr %2, align 4
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store i64 %8, ptr %3, align 8
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%9 = load i64, ptr %3, align 8
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ret i64 %9
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}
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