a64b3e92c7
Previously we returned i32 on RV32 and i64 on RV64. The instructions only consume 32 bits and only produce 32 bits. For RV64, the result is sign extended to 64 bits like *W instructions. This patch removes this detail from the interface to improve portability and consistency. This matches the proposal for scalar intrinsics here https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44 I've included IR autoupgrade support as well. I'll be doing this for other builtins/intrinsics that currently use 'long' in other patches. Reviewed By: VincentWu Differential Revision: https://reviews.llvm.org/D154647
26 lines
749 B
LLVM
26 lines
749 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=riscv64 -mattr=+zksh -verify-machineinstrs < %s \
|
|
; RUN: | FileCheck %s -check-prefix=RV64ZKSH
|
|
|
|
declare i32 @llvm.riscv.sm3p0(i32);
|
|
|
|
define signext i32 @sm3p0_i32(i32 signext %a) nounwind {
|
|
; RV64ZKSH-LABEL: sm3p0_i32:
|
|
; RV64ZKSH: # %bb.0:
|
|
; RV64ZKSH-NEXT: sm3p0 a0, a0
|
|
; RV64ZKSH-NEXT: ret
|
|
%val = call i32 @llvm.riscv.sm3p0(i32 signext %a)
|
|
ret i32 %val
|
|
}
|
|
|
|
declare i32 @llvm.riscv.sm3p1(i32);
|
|
|
|
define signext i32 @sm3p1_i32(i32 signext %a) nounwind {
|
|
; RV64ZKSH-LABEL: sm3p1_i32:
|
|
; RV64ZKSH: # %bb.0:
|
|
; RV64ZKSH-NEXT: sm3p1 a0, a0
|
|
; RV64ZKSH-NEXT: ret
|
|
%val = call i32 @llvm.riscv.sm3p1(i32 signext %a)
|
|
ret i32 %val
|
|
}
|