8624075105
The motivation of this change is simply to reduce test duplication. As can be seen in the (massive) test delta, we have many tests whose output differ only due to the use of addi on rv32 vs addiw on rv64 when the high bits are don't care. As an aside, we don't need to worry about the non-zero immediate restriction on the compressed variants because we're not directly forming the compressed variants. If we happen to get a zero immediate for the ADDI, then either a later optimization will strip the useless instruction or the encoder is responsible for not compressing the instruction.
153 lines
3.9 KiB
LLVM
153 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I
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define i32 @from_cmpeq(i32 %xx, i32 %y) {
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; RV32I-LABEL: from_cmpeq:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, -9
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; RV32I-NEXT: seqz a0, a0
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: from_cmpeq:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: addi a0, a0, -9
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; RV64I-NEXT: seqz a0, a0
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: ret
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%x = icmp eq i32 %xx, 9
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%masked = and i32 %y, 1
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%r = select i1 %x, i32 %masked, i32 0
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ret i32 %r
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}
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define i32 @from_cmpeq_fail_bad_andmask(i32 %xx, i32 %y) {
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; RV32I-LABEL: from_cmpeq_fail_bad_andmask:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, -9
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; RV32I-NEXT: snez a0, a0
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: and a0, a1, a0
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; RV32I-NEXT: andi a0, a0, 3
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: from_cmpeq_fail_bad_andmask:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: addi a0, a0, -9
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; RV64I-NEXT: snez a0, a0
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: and a0, a1, a0
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; RV64I-NEXT: andi a0, a0, 3
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; RV64I-NEXT: ret
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%x = icmp eq i32 %xx, 9
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%masked = and i32 %y, 3
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%r = select i1 %x, i32 %masked, i32 0
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ret i32 %r
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}
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define i32 @from_i1(i1 %x, i32 %y) {
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; RV32I-LABEL: from_i1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: from_i1:
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; RV64I: # %bb.0:
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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%masked = and i32 %y, 1
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%r = select i1 %x, i32 %masked, i32 0
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ret i32 %r
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}
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define i32 @from_trunc_i8(i8 %xx, i32 %y) {
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; RV32I-LABEL: from_trunc_i8:
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; RV32I: # %bb.0:
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: from_trunc_i8:
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; RV64I: # %bb.0:
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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%masked = and i32 %y, 1
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%x = trunc i8 %xx to i1
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%r = select i1 %x, i32 %masked, i32 0
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ret i32 %r
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}
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define i32 @from_trunc_i64(i64 %xx, i32 %y) {
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; RV32I-LABEL: from_trunc_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: from_trunc_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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%masked = and i32 %y, 1
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%x = trunc i64 %xx to i1
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%r = select i1 %x, i32 %masked, i32 0
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ret i32 %r
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}
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define i32 @from_i1_fail_bad_select0(i1 %x, i32 %y) {
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; RV32I-LABEL: from_i1_fail_bad_select0:
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: bnez a0, .LBB5_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: li a0, 1
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB5_2:
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; RV32I-NEXT: andi a0, a1, 1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: from_i1_fail_bad_select0:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: bnez a0, .LBB5_2
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; RV64I-NEXT: # %bb.1:
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; RV64I-NEXT: li a0, 1
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; RV64I-NEXT: ret
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; RV64I-NEXT: .LBB5_2:
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; RV64I-NEXT: andi a0, a1, 1
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; RV64I-NEXT: ret
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%masked = and i32 %y, 1
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%r = select i1 %x, i32 %masked, i32 1
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ret i32 %r
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}
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define i32 @from_i1_fail_bad_select1(i1 %x, i32 %y) {
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; RV32I-LABEL: from_i1_fail_bad_select1:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, -1
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; RV32I-NEXT: and a0, a1, a0
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; RV32I-NEXT: andi a0, a0, 1
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: from_i1_fail_bad_select1:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, a0, -1
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; RV64I-NEXT: and a0, a1, a0
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; RV64I-NEXT: andi a0, a0, 1
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; RV64I-NEXT: ret
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%masked = and i32 %y, 1
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%r = select i1 %x, i32 0, i32 %masked
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ret i32 %r
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}
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