4c97c5131f
This patch adds instruction selection patterns for generating the long immediate arithmetic instructions. We prefer generating instructions that have a 26 bit immediate to a 32 bit immediate given that both are of the same size but the former might be easier to register allocate for. Base RISC-V arithmetic instructions will be preferred, when applicable.
109 lines
3.1 KiB
LLVM
109 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; Test that we are able to generate the Xqcilia instructions
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; RUN: llc < %s -mtriple=riscv32 | FileCheck %s -check-prefix=RV32I
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; RUN: llc < %s -mtriple=riscv32 -mattr=+experimental-xqcilia | FileCheck %s -check-prefix=RV32XQCILIA
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define i32 @add(i32 %a, i32 %b) {
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; RV32I-LABEL: add:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 65536
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; RV32I-NEXT: add a0, a0, a2
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; RV32I-NEXT: lui a2, 573
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; RV32I-NEXT: addi a2, a2, -1330
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; RV32I-NEXT: add a1, a1, a2
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; RV32I-NEXT: and a0, a1, a0
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; RV32I-NEXT: addi a0, a0, 13
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; RV32I-NEXT: ret
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;
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; RV32XQCILIA-LABEL: add:
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; RV32XQCILIA: # %bb.0:
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; RV32XQCILIA-NEXT: qc.e.addi a1, a1, 2345678
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; RV32XQCILIA-NEXT: qc.e.addai a0, 268435456
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; RV32XQCILIA-NEXT: and a0, a0, a1
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; RV32XQCILIA-NEXT: addi a0, a0, 13
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; RV32XQCILIA-NEXT: ret
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%addai = add i32 %a, 268435456
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%add = add i32 %b, 2345678
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%and = and i32 %add, %addai
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%res = add i32 %and, 13
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ret i32 %res
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}
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define i32 @and(i32 %a, i32 %b) {
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; RV32I-LABEL: and:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 65536
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: lui a2, 573
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; RV32I-NEXT: addi a2, a2, -1330
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; RV32I-NEXT: and a1, a1, a2
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; RV32I-NEXT: srl a0, a1, a0
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; RV32I-NEXT: andi a0, a0, 10
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; RV32I-NEXT: ret
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;
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; RV32XQCILIA-LABEL: and:
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; RV32XQCILIA: # %bb.0:
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; RV32XQCILIA-NEXT: qc.e.andi a1, a1, 2345678
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; RV32XQCILIA-NEXT: qc.e.andai a0, 268435456
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; RV32XQCILIA-NEXT: srl a0, a1, a0
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; RV32XQCILIA-NEXT: andi a0, a0, 10
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; RV32XQCILIA-NEXT: ret
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%andai = and i32 %a, 268435456
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%and = and i32 %b, 2345678
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%srl = lshr i32 %and, %andai
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%res = and i32 %srl, 10
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ret i32 %res
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}
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define i32 @or(i32 %a, i32 %b) {
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; RV32I-LABEL: or:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 65536
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; RV32I-NEXT: or a0, a0, a2
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; RV32I-NEXT: lui a2, 573
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; RV32I-NEXT: addi a2, a2, -1330
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; RV32I-NEXT: or a1, a1, a2
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; RV32I-NEXT: add a0, a1, a0
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; RV32I-NEXT: ori a0, a0, 13
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; RV32I-NEXT: ret
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;
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; RV32XQCILIA-LABEL: or:
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; RV32XQCILIA: # %bb.0:
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; RV32XQCILIA-NEXT: qc.e.ori a1, a1, 2345678
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; RV32XQCILIA-NEXT: qc.e.orai a0, 268435456
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; RV32XQCILIA-NEXT: add a0, a0, a1
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; RV32XQCILIA-NEXT: ori a0, a0, 13
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; RV32XQCILIA-NEXT: ret
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%orai = or i32 %a, 268435456
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%or = or i32 %b, 2345678
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%add = add i32 %or, %orai
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%res = or i32 %add, 13
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ret i32 %res
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}
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define i32 @xor(i32 %a, i32 %b) {
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; RV32I-LABEL: xor:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 65536
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; RV32I-NEXT: xor a0, a0, a2
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; RV32I-NEXT: lui a2, 573
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; RV32I-NEXT: addi a2, a2, -1330
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; RV32I-NEXT: xor a1, a1, a2
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; RV32I-NEXT: add a0, a1, a0
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; RV32I-NEXT: xori a0, a0, 13
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; RV32I-NEXT: ret
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;
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; RV32XQCILIA-LABEL: xor:
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; RV32XQCILIA: # %bb.0:
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; RV32XQCILIA-NEXT: qc.e.xori a1, a1, 2345678
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; RV32XQCILIA-NEXT: qc.e.xorai a0, 268435456
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; RV32XQCILIA-NEXT: add a0, a0, a1
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; RV32XQCILIA-NEXT: xori a0, a0, 13
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; RV32XQCILIA-NEXT: ret
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%xorai = xor i32 %a, 268435456
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%xor = xor i32 %b, 2345678
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%add = add i32 %xor, %xorai
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%res = xor i32 %add, 13
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ret i32 %res
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}
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