c9714d2035
-Only fold if the ADD can be folded into all uses. -Don't reassociate an ADDI if the shl+add can be a shxadd or similar instruction. -Only reassociate a single ADDI. If there are 2 addis it's the same number of instructions as shl+add. If there are more than 2 that it would increase instructions over folding the addis into the loads/stores.
516 lines
14 KiB
LLVM
516 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32I
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; RUN: llc -mtriple=riscv32 --mattr=+zba -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32IZBA
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; RUN: llc -mtriple=riscv32 -mattr=+zba,+experimental-xqcisls -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefixes=RV32IZBAXQCISLS
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define i32 @lb_ri(i8* %a, i32 %b) {
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; RV32I-LABEL: lb_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a1, 3
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lb a0, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: lb_ri:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: sh3add a0, a1, a0
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; RV32IZBA-NEXT: lb a0, 0(a0)
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: lb_ri:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: qc.lrb a0, a0, a1, 3
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; RV32IZBAXQCISLS-NEXT: ret
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%shl = shl i32 %b, 3
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%1 = getelementptr i8, i8* %a, i32 %shl
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%2 = load i8, i8* %1
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%3 = sext i8 %2 to i32
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ret i32 %3
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}
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define i32 @lbu_ri(i8* %a, i32 %b) {
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; RV32I-LABEL: lbu_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a1, 2
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lbu a0, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: lbu_ri:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: sh2add a0, a1, a0
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; RV32IZBA-NEXT: lbu a0, 0(a0)
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: lbu_ri:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: qc.lrbu a0, a0, a1, 2
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; RV32IZBAXQCISLS-NEXT: ret
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%shl = shl i32 %b, 2
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%1 = getelementptr i8, i8* %a, i32 %shl
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%2 = load i8, i8* %1
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%3 = zext i8 %2 to i32
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ret i32 %3
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}
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define i32 @lh_ri(i16* %a, i32 %b) {
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; RV32I-LABEL: lh_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a1, 5
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lh a0, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: lh_ri:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: slli a1, a1, 5
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; RV32IZBA-NEXT: add a0, a0, a1
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; RV32IZBA-NEXT: lh a0, 0(a0)
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: lh_ri:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: qc.lrh a0, a0, a1, 5
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; RV32IZBAXQCISLS-NEXT: ret
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%shl = shl i32 %b, 4
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%1 = getelementptr i16, i16* %a, i32 %shl
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%2 = load i16, i16* %1
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%3 = sext i16 %2 to i32
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ret i32 %3
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}
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define i32 @lhu_ri(i16* %a, i32 %b) {
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; RV32I-LABEL: lhu_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a1, 6
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lhu a0, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: lhu_ri:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: slli a1, a1, 6
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; RV32IZBA-NEXT: add a0, a0, a1
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; RV32IZBA-NEXT: lhu a0, 0(a0)
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: lhu_ri:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: qc.lrhu a0, a0, a1, 6
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; RV32IZBAXQCISLS-NEXT: ret
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%shl = shl i32 %b, 5
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%1 = getelementptr i16, i16* %a, i32 %shl
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%2 = load i16, i16* %1
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%3 = zext i16 %2 to i32
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ret i32 %3
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}
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define i32 @lw_ri(i32* %a, i32 %b) {
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; RV32I-LABEL: lw_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a1, 6
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lw a0, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: lw_ri:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: slli a1, a1, 6
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; RV32IZBA-NEXT: add a0, a0, a1
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; RV32IZBA-NEXT: lw a0, 0(a0)
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: lw_ri:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: qc.lrw a0, a0, a1, 6
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; RV32IZBAXQCISLS-NEXT: ret
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%shl = shl i32 %b, 4
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%1 = getelementptr i32, i32* %a, i32 %shl
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%2 = load i32, i32* %1
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ret i32 %2
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}
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define void @sb_ri(i8* %a, i8 %b, i32 %c) {
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; RV32I-LABEL: sb_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a2, a2, 7
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; RV32I-NEXT: add a0, a0, a2
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; RV32I-NEXT: sb a1, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: sb_ri:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: slli a2, a2, 7
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; RV32IZBA-NEXT: add a0, a0, a2
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; RV32IZBA-NEXT: sb a1, 0(a0)
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: sb_ri:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: qc.srb a1, a0, a2, 7
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; RV32IZBAXQCISLS-NEXT: ret
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%shl = shl i32 %c, 7
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%1 = getelementptr i8, i8* %a, i32 %shl
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store i8 %b, i8* %1
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ret void
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}
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define void @sh_ri(i16* %a, i16 %b, i32 %c) {
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; RV32I-LABEL: sh_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a2, a2, 3
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; RV32I-NEXT: add a0, a0, a2
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; RV32I-NEXT: sh a1, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: sh_ri:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: sh3add a0, a2, a0
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; RV32IZBA-NEXT: sh a1, 0(a0)
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: sh_ri:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: qc.srh a1, a0, a2, 3
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; RV32IZBAXQCISLS-NEXT: ret
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%shl = shl i32 %c, 2
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%1 = getelementptr i16, i16* %a, i32 %shl
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store i16 %b, i16* %1
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ret void
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}
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define void @sw_ri(i32* %a, i32 %b, i32 %c) {
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; RV32I-LABEL: sw_ri:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a2, a2, 3
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; RV32I-NEXT: add a0, a0, a2
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; RV32I-NEXT: sw a1, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: sw_ri:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: sh3add a0, a2, a0
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; RV32IZBA-NEXT: sw a1, 0(a0)
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: sw_ri:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: qc.srw a1, a0, a2, 3
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; RV32IZBAXQCISLS-NEXT: ret
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%shl = shl i32 %c, 1
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%1 = getelementptr i32, i32* %a, i32 %shl
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store i32 %b, i32* %1
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ret void
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}
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define i8 @lrb_anyext(ptr %a, i32 %b) {
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; RV32I-LABEL: lrb_anyext:
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; RV32I: # %bb.0:
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lbu a0, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: lrb_anyext:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: add a0, a0, a1
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; RV32IZBA-NEXT: lbu a0, 0(a0)
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: lrb_anyext:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: qc.lrbu a0, a0, a1, 0
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; RV32IZBAXQCISLS-NEXT: ret
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%1 = getelementptr i8, ptr %a, i32 %b
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%2 = load i8, ptr %1, align 1
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ret i8 %2
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}
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define i32 @lrb(ptr %a, i32 %b) {
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; RV32I-LABEL: lrb:
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; RV32I: # %bb.0:
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lb a0, 0(a0)
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; RV32I-NEXT: add a0, a0, a0
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: lrb:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: add a0, a0, a1
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; RV32IZBA-NEXT: lb a0, 0(a0)
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; RV32IZBA-NEXT: add a0, a0, a0
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: lrb:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: qc.lrb a0, a0, a1, 0
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; RV32IZBAXQCISLS-NEXT: add a0, a0, a0
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; RV32IZBAXQCISLS-NEXT: ret
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%1 = getelementptr i8, ptr %a, i32 %b
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%2 = load i8, ptr %1, align 1
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%3 = sext i8 %2 to i32
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%4 = add i32 %3, %3
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ret i32 %4
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}
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define i32 @lrbu(ptr %a, i32 %b) {
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; RV32I-LABEL: lrbu:
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; RV32I: # %bb.0:
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lbu a0, 0(a0)
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; RV32I-NEXT: add a0, a0, a0
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: lrbu:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: add a0, a0, a1
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; RV32IZBA-NEXT: lbu a0, 0(a0)
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; RV32IZBA-NEXT: add a0, a0, a0
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: lrbu:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: qc.lrbu a0, a0, a1, 0
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; RV32IZBAXQCISLS-NEXT: add a0, a0, a0
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; RV32IZBAXQCISLS-NEXT: ret
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%1 = getelementptr i8, ptr %a, i32 %b
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%2 = load i8, ptr %1, align 1
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%3 = zext i8 %2 to i32
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%4 = add i32 %3, %3
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ret i32 %4
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}
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define i64 @lrd(ptr %a, i32 %b) {
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; RV32I-LABEL: lrd:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a1, 3
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: lw a1, 0(a0)
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; RV32I-NEXT: lw a2, 4(a0)
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; RV32I-NEXT: add a0, a1, a1
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; RV32I-NEXT: sltu a1, a0, a1
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; RV32I-NEXT: add a2, a2, a2
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; RV32I-NEXT: add a1, a2, a1
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: lrd:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: sh3add a0, a1, a0
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; RV32IZBA-NEXT: lw a1, 0(a0)
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; RV32IZBA-NEXT: lw a2, 4(a0)
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; RV32IZBA-NEXT: add a0, a1, a1
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; RV32IZBA-NEXT: sltu a1, a0, a1
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; RV32IZBA-NEXT: add a2, a2, a2
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; RV32IZBA-NEXT: add a1, a2, a1
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: lrd:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: sh3add a0, a1, a0
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; RV32IZBAXQCISLS-NEXT: lw a1, 0(a0)
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; RV32IZBAXQCISLS-NEXT: lw a2, 4(a0)
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; RV32IZBAXQCISLS-NEXT: add a0, a1, a1
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; RV32IZBAXQCISLS-NEXT: sltu a1, a0, a1
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; RV32IZBAXQCISLS-NEXT: add a2, a2, a2
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; RV32IZBAXQCISLS-NEXT: add a1, a2, a1
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; RV32IZBAXQCISLS-NEXT: ret
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%1 = getelementptr i64, ptr %a, i32 %b
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%2 = load i64, ptr %1, align 8
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%3 = add i64 %2, %2
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ret i64 %3
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}
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define i64 @lrd_2(ptr %a, i32 %b) {
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; RV32I-LABEL: lrd_2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a1, a1, 3
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; RV32I-NEXT: add a0, a1, a0
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; RV32I-NEXT: lw a1, 96(a0)
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; RV32I-NEXT: lw a2, 100(a0)
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; RV32I-NEXT: add a0, a1, a1
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; RV32I-NEXT: sltu a1, a0, a1
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; RV32I-NEXT: add a2, a2, a2
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; RV32I-NEXT: add a1, a2, a1
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: lrd_2:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: sh3add a0, a1, a0
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; RV32IZBA-NEXT: lw a1, 96(a0)
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; RV32IZBA-NEXT: lw a2, 100(a0)
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; RV32IZBA-NEXT: add a0, a1, a1
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; RV32IZBA-NEXT: sltu a1, a0, a1
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; RV32IZBA-NEXT: add a2, a2, a2
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; RV32IZBA-NEXT: add a1, a2, a1
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: lrd_2:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: sh3add a0, a1, a0
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; RV32IZBAXQCISLS-NEXT: lw a1, 96(a0)
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; RV32IZBAXQCISLS-NEXT: lw a2, 100(a0)
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; RV32IZBAXQCISLS-NEXT: add a0, a1, a1
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; RV32IZBAXQCISLS-NEXT: sltu a1, a0, a1
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; RV32IZBAXQCISLS-NEXT: add a2, a2, a2
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; RV32IZBAXQCISLS-NEXT: add a1, a2, a1
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; RV32IZBAXQCISLS-NEXT: ret
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%1 = add i32 %b, 12
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%2 = getelementptr i64, ptr %a, i32 %1
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%3 = load i64, ptr %2, align 8
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%4 = add i64 %3, %3
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ret i64 %4
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}
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define void @srb(ptr %a, i32 %b, i8 %c) {
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; RV32I-LABEL: srb:
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; RV32I: # %bb.0:
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; RV32I-NEXT: add a2, a2, a2
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: sb a2, 0(a0)
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; RV32I-NEXT: ret
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;
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; RV32IZBA-LABEL: srb:
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; RV32IZBA: # %bb.0:
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; RV32IZBA-NEXT: add a2, a2, a2
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; RV32IZBA-NEXT: add a0, a0, a1
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; RV32IZBA-NEXT: sb a2, 0(a0)
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; RV32IZBA-NEXT: ret
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;
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; RV32IZBAXQCISLS-LABEL: srb:
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; RV32IZBAXQCISLS: # %bb.0:
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; RV32IZBAXQCISLS-NEXT: add a2, a2, a2
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; RV32IZBAXQCISLS-NEXT: qc.srb a2, a0, a1, 0
|
|
; RV32IZBAXQCISLS-NEXT: ret
|
|
%1 = add i8 %c, %c
|
|
%2 = getelementptr i8, ptr %a, i32 %b
|
|
store i8 %1, ptr %2, align 1
|
|
ret void
|
|
}
|
|
|
|
define void @srh(ptr %a, i32 %b, i16 %c) {
|
|
; RV32I-LABEL: srh:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: add a2, a2, a2
|
|
; RV32I-NEXT: slli a1, a1, 1
|
|
; RV32I-NEXT: add a0, a0, a1
|
|
; RV32I-NEXT: sh a2, 0(a0)
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IZBA-LABEL: srh:
|
|
; RV32IZBA: # %bb.0:
|
|
; RV32IZBA-NEXT: add a2, a2, a2
|
|
; RV32IZBA-NEXT: sh1add a0, a1, a0
|
|
; RV32IZBA-NEXT: sh a2, 0(a0)
|
|
; RV32IZBA-NEXT: ret
|
|
;
|
|
; RV32IZBAXQCISLS-LABEL: srh:
|
|
; RV32IZBAXQCISLS: # %bb.0:
|
|
; RV32IZBAXQCISLS-NEXT: add a2, a2, a2
|
|
; RV32IZBAXQCISLS-NEXT: qc.srh a2, a0, a1, 1
|
|
; RV32IZBAXQCISLS-NEXT: ret
|
|
%1 = add i16 %c, %c
|
|
%2 = getelementptr i16, ptr %a, i32 %b
|
|
store i16 %1, ptr %2, align 2
|
|
ret void
|
|
}
|
|
|
|
define void @srw(ptr %a, i32 %b, i32 %c) {
|
|
; RV32I-LABEL: srw:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: add a2, a2, a2
|
|
; RV32I-NEXT: slli a1, a1, 2
|
|
; RV32I-NEXT: add a0, a0, a1
|
|
; RV32I-NEXT: sw a2, 0(a0)
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IZBA-LABEL: srw:
|
|
; RV32IZBA: # %bb.0:
|
|
; RV32IZBA-NEXT: add a2, a2, a2
|
|
; RV32IZBA-NEXT: sh2add a0, a1, a0
|
|
; RV32IZBA-NEXT: sw a2, 0(a0)
|
|
; RV32IZBA-NEXT: ret
|
|
;
|
|
; RV32IZBAXQCISLS-LABEL: srw:
|
|
; RV32IZBAXQCISLS: # %bb.0:
|
|
; RV32IZBAXQCISLS-NEXT: add a2, a2, a2
|
|
; RV32IZBAXQCISLS-NEXT: qc.srw a2, a0, a1, 2
|
|
; RV32IZBAXQCISLS-NEXT: ret
|
|
%1 = add i32 %c, %c
|
|
%2 = getelementptr i32, ptr %a, i32 %b
|
|
store i32 %1, ptr %2, align 4
|
|
ret void
|
|
}
|
|
|
|
define void @srd(ptr %a, i32 %b, i64 %c) {
|
|
; RV32I-LABEL: srd:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: add a4, a2, a2
|
|
; RV32I-NEXT: add a3, a3, a3
|
|
; RV32I-NEXT: slli a1, a1, 3
|
|
; RV32I-NEXT: sltu a2, a4, a2
|
|
; RV32I-NEXT: add a0, a0, a1
|
|
; RV32I-NEXT: add a2, a3, a2
|
|
; RV32I-NEXT: sw a4, 0(a0)
|
|
; RV32I-NEXT: sw a2, 4(a0)
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IZBA-LABEL: srd:
|
|
; RV32IZBA: # %bb.0:
|
|
; RV32IZBA-NEXT: add a4, a2, a2
|
|
; RV32IZBA-NEXT: add a3, a3, a3
|
|
; RV32IZBA-NEXT: sh3add a0, a1, a0
|
|
; RV32IZBA-NEXT: sltu a1, a4, a2
|
|
; RV32IZBA-NEXT: add a1, a3, a1
|
|
; RV32IZBA-NEXT: sw a4, 0(a0)
|
|
; RV32IZBA-NEXT: sw a1, 4(a0)
|
|
; RV32IZBA-NEXT: ret
|
|
;
|
|
; RV32IZBAXQCISLS-LABEL: srd:
|
|
; RV32IZBAXQCISLS: # %bb.0:
|
|
; RV32IZBAXQCISLS-NEXT: add a4, a2, a2
|
|
; RV32IZBAXQCISLS-NEXT: add a3, a3, a3
|
|
; RV32IZBAXQCISLS-NEXT: sh3add a0, a1, a0
|
|
; RV32IZBAXQCISLS-NEXT: sltu a1, a4, a2
|
|
; RV32IZBAXQCISLS-NEXT: add a1, a3, a1
|
|
; RV32IZBAXQCISLS-NEXT: sw a4, 0(a0)
|
|
; RV32IZBAXQCISLS-NEXT: sw a1, 4(a0)
|
|
; RV32IZBAXQCISLS-NEXT: ret
|
|
%1 = add i64 %c, %c
|
|
%2 = getelementptr i64, ptr %a, i32 %b
|
|
store i64 %1, ptr %2, align 8
|
|
ret void
|
|
}
|
|
|
|
define i64 @lrd_large_shift(ptr %a, i32 %b) {
|
|
; RV32I-LABEL: lrd_large_shift:
|
|
; RV32I: # %bb.0:
|
|
; RV32I-NEXT: slli a1, a1, 5
|
|
; RV32I-NEXT: add a1, a1, a0
|
|
; RV32I-NEXT: lw a0, 384(a1)
|
|
; RV32I-NEXT: lw a1, 388(a1)
|
|
; RV32I-NEXT: ret
|
|
;
|
|
; RV32IZBA-LABEL: lrd_large_shift:
|
|
; RV32IZBA: # %bb.0:
|
|
; RV32IZBA-NEXT: slli a1, a1, 5
|
|
; RV32IZBA-NEXT: add a1, a1, a0
|
|
; RV32IZBA-NEXT: lw a0, 384(a1)
|
|
; RV32IZBA-NEXT: lw a1, 388(a1)
|
|
; RV32IZBA-NEXT: ret
|
|
;
|
|
; RV32IZBAXQCISLS-LABEL: lrd_large_shift:
|
|
; RV32IZBAXQCISLS: # %bb.0:
|
|
; RV32IZBAXQCISLS-NEXT: slli a1, a1, 5
|
|
; RV32IZBAXQCISLS-NEXT: add a1, a1, a0
|
|
; RV32IZBAXQCISLS-NEXT: lw a0, 384(a1)
|
|
; RV32IZBAXQCISLS-NEXT: lw a1, 388(a1)
|
|
; RV32IZBAXQCISLS-NEXT: ret
|
|
%1 = add i32 %b, 12
|
|
%2 = shl i32 %1, 2
|
|
%3 = getelementptr i64, ptr %a, i32 %2
|
|
%4 = load i64, ptr %3, align 8
|
|
ret i64 %4
|
|
}
|