67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
57 lines
1.9 KiB
LLVM
57 lines
1.9 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefix=CHECK-SPIRV
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; CHECK-SPIRV-NOT: OpCapability ExpectAssumeKHR
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; CHECK-SPIRV-NOT: OpExtension "SPV_KHR_expect_assume"
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; CHECK-SPIRV: OpName %[[#COMPARE:]] "cmp"
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; CHECK-SPIRV: %[[#COMPARE]] = OpINotEqual %[[#]] %[[#]] %[[#]]
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; CHECK-SPIRV-NOT: OpAssumeTrueKHR %[[#COMPARE]]
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%class.anon = type { i8 }
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define spir_func void @_Z3fooi(i32 %x) {
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entry:
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%0 = load i32, i32* %x.addr, align 4
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%cmp = icmp ne i32 %0, 0
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call void @llvm.assume(i1 %cmp)
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ret void
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}
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declare void @llvm.assume(i1)
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define i32 @main() {
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entry:
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%retval = alloca i32, align 4
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%agg.tmp = alloca %class.anon, align 1
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store i32 0, i32* %retval, align 4
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call spir_func void @"_Z18kernel_single_taskIZ4mainE11fake_kernelZ4mainE3$_0EvT0_"(%class.anon* byval(%class.anon) align 1 %agg.tmp)
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ret i32 0
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}
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define internal spir_func void @"_Z18kernel_single_taskIZ4mainE11fake_kernelZ4mainE3$_0EvT0_"(%class.anon* byval(%class.anon) align 1 %kernelFunc) {
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entry:
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call spir_func void @"_ZZ4mainENK3$_0clEv"(%class.anon* %kernelFunc)
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ret void
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}
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define internal spir_func void @"_ZZ4mainENK3$_0clEv"(%class.anon* %this) align 2 {
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entry:
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%this.addr = alloca %class.anon*, align 8
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%a = alloca i32, align 4
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store %class.anon* %this, %class.anon** %this.addr, align 8
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%this1 = load %class.anon*, %class.anon** %this.addr, align 8
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%0 = bitcast i32* %a to i8*
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call void @llvm.lifetime.start.p0i8(i64 4, i8* %0)
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store i32 1, i32* %a, align 4
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%1 = load i32, i32* %a, align 4
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call spir_func void @_Z3fooi(i32 %1)
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%2 = bitcast i32* %a to i8*
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call void @llvm.lifetime.end.p0i8(i64 4, i8* %2)
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ret void
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}
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declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
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declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
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