67d3ef74b3
This PR continues https://github.com/llvm/llvm-project/pull/101732 changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. Namely, the following changes are introduced: * register classes (lib/Target/SPIRV/SPIRVRegisterInfo.td) and instruction patterns (lib/Target/SPIRV/SPIRVInstrInfo.td) are corrected and simplified (by removing unnecessary sophisticated options) -- e.g., this PR gets rid of duplicating 32/64 bits patterns, removes ANYID register class and simplifies definition of the rest of register classes, * hardcoded LLT scalar types in passes before instruction selection are corrected -- the goal is to have correct bit width before instruction selection, and use 64 bits registers for pattern matching in the instruction selection pass; 32-bit registers remain where they are described in such terms by SPIR-V specification (like, for example, creation of virtual registers for scope/mem semantics operands), * rework virtual register type/class assignment for calls/builtins lowering, * a series of minor changes to fix validity of emitted code between passes: - ensure that that bitcast changes the type, - fix the pattern for instruction selection for OpExtInst, - simplify inline asm operands usage, - account for arbitrary integer sizes / update legalizer rules; * add '-verify-machineinstrs' to existed test cases. See also https://github.com/llvm/llvm-project/issues/88129 that this PR may resolve. This PR fixes a great number of issues reported by MachineVerifier and, as a result, reduces a number of failed test cases for the mode with expensive checks set on from ~200 to ~57.
57 lines
1.5 KiB
LLVM
57 lines
1.5 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
|
|
|
|
; CHECK: %[[#extinst_id:]] = OpExtInstImport "OpenCL.std"
|
|
|
|
; CHECK: %[[#var0:]] = OpTypeFloat 16
|
|
; CHECK: %[[#var1:]] = OpTypeFloat 32
|
|
; CHECK: %[[#var2:]] = OpTypeFloat 64
|
|
; CHECK: %[[#var3:]] = OpTypeVector %[[#var1]] 4
|
|
|
|
; CHECK: OpFunction
|
|
; CHECK: %[[#]] = OpExtInst %[[#var0]] %[[#extinst_id]] fabs
|
|
; CHECK: OpFunctionEnd
|
|
|
|
define spir_func half @TestFabs16(half %x) local_unnamed_addr {
|
|
entry:
|
|
%0 = tail call half @llvm.fabs.f16(half %x)
|
|
ret half %0
|
|
}
|
|
|
|
; CHECK: OpFunction
|
|
; CHECK: %[[#]] = OpExtInst %[[#var1]] %[[#extinst_id]] fabs
|
|
; CHECK: OpFunctionEnd
|
|
|
|
define spir_func float @TestFabs32(float %x) local_unnamed_addr {
|
|
entry:
|
|
%0 = tail call float @llvm.fabs.f32(float %x)
|
|
ret float %0
|
|
}
|
|
|
|
; CHECK: OpFunction
|
|
; CHECK: %[[#]] = OpExtInst %[[#var2]] %[[#extinst_id]] fabs
|
|
; CHECK: OpFunctionEnd
|
|
|
|
define spir_func double @TestFabs64(double %x) local_unnamed_addr {
|
|
entry:
|
|
%0 = tail call double @llvm.fabs.f64(double %x)
|
|
ret double %0
|
|
}
|
|
|
|
; CHECK: OpFunction
|
|
; CHECK: %[[#]] = OpExtInst %[[#var3]] %[[#extinst_id]] fabs
|
|
; CHECK: OpFunctionEnd
|
|
|
|
define spir_func <4 x float> @TestFabsVec(<4 x float> %x) local_unnamed_addr {
|
|
entry:
|
|
%0 = tail call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
|
|
ret <4 x float> %0
|
|
}
|
|
|
|
declare half @llvm.fabs.f16(half)
|
|
|
|
declare float @llvm.fabs.f32(float)
|
|
|
|
declare double @llvm.fabs.f64(double)
|
|
|
|
declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
|