36d757f840
Fixes #88052 - Added the following intrinsics: - `int_spv_uclamp` - `int_spv_sclamp` - `int_spv_fclamp` - Updated DirectX counterparts to have the same three clamp intrinsics. - Update the clamp.hlsl unit tests to include SPIRV - Added the SPIRV specific tests
243 lines
12 KiB
LLVM
243 lines
12 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
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; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %}
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; CHECK-DAG: %[[#op_ext:]] = OpExtInstImport "OpenCL.std"
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; CHECK-DAG: %[[#float_64:]] = OpTypeFloat 64
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; CHECK-DAG: %[[#float_32:]] = OpTypeFloat 32
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; CHECK-DAG: %[[#float_16:]] = OpTypeFloat 16
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; CHECK-DAG: %[[#int_64:]] = OpTypeInt 64
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; CHECK-DAG: %[[#int_32:]] = OpTypeInt 32
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; CHECK-DAG: %[[#int_16:]] = OpTypeInt 16
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; CHECK-DAG: %[[#vec4_float_64:]] = OpTypeVector %[[#float_64]] 4
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; CHECK-DAG: %[[#vec4_float_32:]] = OpTypeVector %[[#float_32]] 4
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; CHECK-DAG: %[[#vec4_float_16:]] = OpTypeVector %[[#float_16]] 4
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; CHECK-DAG: %[[#vec4_int_64:]] = OpTypeVector %[[#int_64]] 4
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; CHECK-DAG: %[[#vec4_int_32:]] = OpTypeVector %[[#int_32]] 4
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; CHECK-DAG: %[[#vec4_int_16:]] = OpTypeVector %[[#int_16]] 4
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; CHECK-LABEL: Begin function test_sclamp_i16
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define noundef i16 @test_sclamp_i16(i16 noundef %a, i16 noundef %b, i16 noundef %c) {
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entry:
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; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
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; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
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; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
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; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] s_clamp %[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]]
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%0 = call i16 @llvm.spv.sclamp.i16(i16 %a, i16 %b, i16 %c)
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ret i16 %0
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}
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; CHECK-LABEL: Begin function test_sclamp_i32
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define noundef i32 @test_sclamp_i32(i32 noundef %a, i32 noundef %b, i32 noundef %c) {
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entry:
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; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
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; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
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; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
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; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] s_clamp %[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]]
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%0 = call i32 @llvm.spv.sclamp.i32(i32 %a, i32 %b, i32 %c)
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ret i32 %0
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}
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; CHECK-LABEL: Begin function test_sclamp_i64
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define noundef i64 @test_sclamp_i64(i64 noundef %a, i64 noundef %b, i64 noundef %c) {
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entry:
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; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
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; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
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; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
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; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] s_clamp %[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]]
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%0 = call i64 @llvm.spv.sclamp.i64(i64 %a, i64 %b, i64 %c)
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ret i64 %0
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}
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; CHECK-LABEL: Begin function test_nclamp_half
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define noundef half @test_nclamp_half(half noundef %a, half noundef %b, half noundef %c) {
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entry:
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; CHECK: %[[#f16_arg0:]] = OpFunctionParameter %[[#float_16]]
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; CHECK: %[[#f16_arg1:]] = OpFunctionParameter %[[#float_16]]
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; CHECK: %[[#f16_arg2:]] = OpFunctionParameter %[[#float_16]]
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; CHECK: %[[#]] = OpExtInst %[[#float_16]] %[[#op_ext]] fclamp %[[#f16_arg0]] %[[#f16_arg1]] %[[#f16_arg2]]
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%0 = call half @llvm.spv.nclamp.f16(half %a, half %b, half %c)
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ret half %0
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}
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; CHECK-LABEL: Begin function test_nclamp_float
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define noundef float @test_nclamp_float(float noundef %a, float noundef %b, float noundef %c) {
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entry:
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; CHECK: %[[#f32_arg0:]] = OpFunctionParameter %[[#float_32]]
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; CHECK: %[[#f32_arg1:]] = OpFunctionParameter %[[#float_32]]
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; CHECK: %[[#f32_arg2:]] = OpFunctionParameter %[[#float_32]]
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; CHECK: %[[#]] = OpExtInst %[[#float_32]] %[[#op_ext]] fclamp %[[#f32_arg0]] %[[#f32_arg1]] %[[#f32_arg2]]
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%0 = call float @llvm.spv.nclamp.f32(float %a, float %b, float %c)
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ret float %0
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}
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; CHECK-LABEL: Begin function test_nclamp_double
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define noundef double @test_nclamp_double(double noundef %a, double noundef %b, double noundef %c) {
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entry:
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; CHECK: %[[#f64_arg0:]] = OpFunctionParameter %[[#float_64]]
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; CHECK: %[[#f64_arg1:]] = OpFunctionParameter %[[#float_64]]
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; CHECK: %[[#f64_arg2:]] = OpFunctionParameter %[[#float_64]]
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; CHECK: %[[#]] = OpExtInst %[[#float_64]] %[[#op_ext]] fclamp %[[#f64_arg0]] %[[#f64_arg1]] %[[#f64_arg2]]
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%0 = call double @llvm.spv.nclamp.f64(double %a, double %b, double %c)
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ret double %0
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}
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; CHECK-LABEL: Begin function test_uclamp_i16
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define noundef i16 @test_uclamp_i16(i16 noundef %a, i16 noundef %b, i16 noundef %c) {
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entry:
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; CHECK: %[[#i16_arg0:]] = OpFunctionParameter %[[#int_16]]
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; CHECK: %[[#i16_arg1:]] = OpFunctionParameter %[[#int_16]]
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; CHECK: %[[#i16_arg2:]] = OpFunctionParameter %[[#int_16]]
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; CHECK: %[[#]] = OpExtInst %[[#int_16]] %[[#op_ext]] u_clamp %[[#i16_arg0]] %[[#i16_arg1]] %[[#i16_arg2]]
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%0 = call i16 @llvm.spv.uclamp.i16(i16 %a, i16 %b, i16 %c)
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ret i16 %0
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}
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; CHECK-LABEL: Begin function test_uclamp_i32
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define noundef i32 @test_uclamp_i32(i32 noundef %a, i32 noundef %b, i32 noundef %c) {
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entry:
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; CHECK: %[[#i32_arg0:]] = OpFunctionParameter %[[#int_32]]
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; CHECK: %[[#i32_arg1:]] = OpFunctionParameter %[[#int_32]]
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; CHECK: %[[#i32_arg2:]] = OpFunctionParameter %[[#int_32]]
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; CHECK: %[[#]] = OpExtInst %[[#int_32]] %[[#op_ext]] u_clamp %[[#i32_arg0]] %[[#i32_arg1]] %[[#i32_arg2]]
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%0 = call i32 @llvm.spv.uclamp.i32(i32 %a, i32 %b, i32 %c)
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ret i32 %0
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}
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; CHECK-LABEL: Begin function test_uclamp_i64
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define noundef i64 @test_uclamp_i64(i64 noundef %a, i64 noundef %b, i64 noundef %c) {
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entry:
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; CHECK: %[[#i64_arg0:]] = OpFunctionParameter %[[#int_64]]
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; CHECK: %[[#i64_arg1:]] = OpFunctionParameter %[[#int_64]]
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; CHECK: %[[#i64_arg2:]] = OpFunctionParameter %[[#int_64]]
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; CHECK: %[[#]] = OpExtInst %[[#int_64]] %[[#op_ext]] u_clamp %[[#i64_arg0]] %[[#i64_arg1]] %[[#i64_arg2]]
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%0 = call i64 @llvm.spv.uclamp.i64(i64 %a, i64 %b, i64 %c)
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ret i64 %0
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}
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declare half @llvm.spv.nclamp.f16(half, half, half)
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declare float @llvm.spv.nclamp.f32(float, float, float)
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declare double @llvm.spv.nclamp.f64(double, double, double)
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declare i16 @llvm.spv.sclamp.i16(i16, i16, i16)
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declare i32 @llvm.spv.sclamp.i32(i32, i32, i32)
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declare i64 @llvm.spv.sclamp.i64(i64, i64, i64)
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declare i16 @llvm.spv.uclamp.i16(i16, i16, i16)
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declare i32 @llvm.spv.uclamp.i32(i32, i32, i32)
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declare i64 @llvm.spv.uclamp.i64(i64, i64, i64)
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; CHECK-LABEL: Begin function test_sclamp_v4i16
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define noundef <4 x i16> @test_sclamp_v4i16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) {
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entry:
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; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
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; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
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; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
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; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] s_clamp %[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
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%0 = call <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c)
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ret <4 x i16> %0
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}
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; CHECK-LABEL: Begin function test_sclamp_v4i32
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define noundef <4 x i32> @test_sclamp_v4i32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) {
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entry:
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; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
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; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
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; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
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; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] s_clamp %[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
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%0 = call <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
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ret <4 x i32> %0
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}
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; CHECK-LABEL: Begin function test_sclamp_v4i64
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define noundef <4 x i64> @test_sclamp_v4i64(<4 x i64> noundef %a, <4 x i64> noundef %b, <4 x i64> noundef %c) {
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entry:
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; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
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; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
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; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
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; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] s_clamp %[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
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%0 = call <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c)
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ret <4 x i64> %0
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}
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; CHECK-LABEL: Begin function test_nclamp_v4half
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define noundef <4 x half> @test_nclamp_v4half(<4 x half> noundef %a, <4 x half> noundef %b, <4 x half> noundef %c) {
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entry:
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; CHECK: %[[#vec4_f16_arg0:]] = OpFunctionParameter %[[#vec4_float_16]]
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; CHECK: %[[#vec4_f16_arg1:]] = OpFunctionParameter %[[#vec4_float_16]]
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; CHECK: %[[#vec4_f16_arg2:]] = OpFunctionParameter %[[#vec4_float_16]]
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; CHECK: %[[#]] = OpExtInst %[[#vec4_float_16]] %[[#op_ext]] fclamp %[[#vec4_f16_arg0]] %[[#vec4_f16_arg1]] %[[#vec4_f16_arg2]]
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%0 = call <4 x half> @llvm.spv.nclamp.v4f16(<4 x half> %a, <4 x half> %b, <4 x half> %c)
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ret <4 x half> %0
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}
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; CHECK-LABEL: Begin function test_nclamp_v4float
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define noundef <4 x float> @test_nclamp_v4float(<4 x float> noundef %a, <4 x float> noundef %b, <4 x float> noundef %c) {
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entry:
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; CHECK: %[[#vec4_f32_arg0:]] = OpFunctionParameter %[[#vec4_float_32]]
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; CHECK: %[[#vec4_f32_arg1:]] = OpFunctionParameter %[[#vec4_float_32]]
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; CHECK: %[[#vec4_f32_arg2:]] = OpFunctionParameter %[[#vec4_float_32]]
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; CHECK: %[[#]] = OpExtInst %[[#vec4_float_32]] %[[#op_ext]] fclamp %[[#vec4_f32_arg0]] %[[#vec4_f32_arg1]] %[[#vec4_f32_arg2]]
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%0 = call <4 x float> @llvm.spv.nclamp.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)
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ret <4 x float> %0
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}
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; CHECK-LABEL: Begin function test_nclamp_v4double
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define noundef <4 x double> @test_nclamp_v4double(<4 x double> noundef %a, <4 x double> noundef %b, <4 x double> noundef %c) {
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entry:
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; CHECK: %[[#vec4_f64_arg0:]] = OpFunctionParameter %[[#vec4_float_64]]
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; CHECK: %[[#vec4_f64_arg1:]] = OpFunctionParameter %[[#vec4_float_64]]
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; CHECK: %[[#vec4_f64_arg2:]] = OpFunctionParameter %[[#vec4_float_64]]
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; CHECK: %[[#]] = OpExtInst %[[#vec4_float_64]] %[[#op_ext]] fclamp %[[#vec4_f64_arg0]] %[[#vec4_f64_arg1]] %[[#vec4_f64_arg2]]
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%0 = call <4 x double> @llvm.spv.nclamp.v4f64(<4 x double> %a, <4 x double> %b, <4 x double> %c)
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ret <4 x double> %0
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}
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; CHECK-LABEL: Begin function test_uclamp_v4i16
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define noundef <4 x i16> @test_uclamp_v4i16(<4 x i16> noundef %a, <4 x i16> noundef %b, <4 x i16> noundef %c) {
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entry:
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; CHECK: %[[#vec4_i16_arg0:]] = OpFunctionParameter %[[#vec4_int_16]]
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; CHECK: %[[#vec4_i16_arg1:]] = OpFunctionParameter %[[#vec4_int_16]]
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; CHECK: %[[#vec4_i16_arg2:]] = OpFunctionParameter %[[#vec4_int_16]]
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; CHECK: %[[#]] = OpExtInst %[[#vec4_int_16]] %[[#op_ext]] u_clamp %[[#vec4_i16_arg0]] %[[#vec4_i16_arg1]] %[[#vec4_i16_arg2]]
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%0 = call <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c)
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ret <4 x i16> %0
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}
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; CHECK-LABEL: Begin function test_uclamp_v4i32
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define noundef <4 x i32> @test_uclamp_v4i32(<4 x i32> noundef %a, <4 x i32> noundef %b, <4 x i32> noundef %c) {
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entry:
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; CHECK: %[[#vec4_i32_arg0:]] = OpFunctionParameter %[[#vec4_int_32]]
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; CHECK: %[[#vec4_i32_arg1:]] = OpFunctionParameter %[[#vec4_int_32]]
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; CHECK: %[[#vec4_i32_arg2:]] = OpFunctionParameter %[[#vec4_int_32]]
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; CHECK: %[[#]] = OpExtInst %[[#vec4_int_32]] %[[#op_ext]] u_clamp %[[#vec4_i32_arg0]] %[[#vec4_i32_arg1]] %[[#vec4_i32_arg2]]
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%0 = call <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c)
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ret <4 x i32> %0
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}
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; CHECK-LABEL: Begin function test_uclamp_v4i64
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define noundef <4 x i64> @test_uclamp_v4i64(<4 x i64> noundef %a, <4 x i64> noundef %b, <4 x i64> noundef %c) {
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entry:
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; CHECK: %[[#vec4_i64_arg0:]] = OpFunctionParameter %[[#vec4_int_64]]
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; CHECK: %[[#vec4_i64_arg1:]] = OpFunctionParameter %[[#vec4_int_64]]
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; CHECK: %[[#vec4_i64_arg2:]] = OpFunctionParameter %[[#vec4_int_64]]
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; CHECK: %[[#]] = OpExtInst %[[#vec4_int_64]] %[[#op_ext]] u_clamp %[[#vec4_i64_arg0]] %[[#vec4_i64_arg1]] %[[#vec4_i64_arg2]]
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%0 = call <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64> %a, <4 x i64> %b, <4 x i64> %c)
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ret <4 x i64> %0
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}
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declare <4 x half> @llvm.spv.nclamp.v4f16(<4 x half>, <4 x half>, <4 x half>)
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declare <4 x float> @llvm.spv.nclamp.v4f32(<4 x float>, <4 x float>, <4 x float>)
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declare <4 x double> @llvm.spv.nclamp.v4f64(<4 x double>, <4 x double>, <4 x double>)
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declare <4 x i16> @llvm.spv.sclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
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declare <4 x i32> @llvm.spv.sclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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declare <4 x i64> @llvm.spv.sclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
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declare <4 x i16> @llvm.spv.uclamp.v4i16(<4 x i16>, <4 x i16>, <4 x i16>)
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declare <4 x i32> @llvm.spv.uclamp.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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declare <4 x i64> @llvm.spv.uclamp.v4i64(<4 x i64>, <4 x i64>, <4 x i64>)
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