80267f8148
The recently announced IBM z17 processor implements the architecture already supported as "arch15" in LLVM. This patch adds support for "z17" as an alternate architecture name for arch15. This patch also add the scheduler description for the z17 processor, provided by Jonas Paulsson.
45 lines
1.6 KiB
LLVM
45 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; Test the handling of i128 argument values
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
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declare void @bar(i64, i64, i64, i64, i128,
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i64, i64, i64, i64, i128)
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; There are two indirect i128 slots, one at offset 200 (the first available
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; byte after the outgoing arguments) and one immediately after it at 216.
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define void @foo() {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r6, %r15, 48(%r15)
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; CHECK-NEXT: .cfi_offset %r6, -112
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -232
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; CHECK-NEXT: .cfi_def_cfa_offset 392
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; CHECK-NEXT: larl %r1, .LCPI0_0
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; CHECK-NEXT: vl %v0, 0(%r1), 3
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; CHECK-NEXT: la %r0, 200(%r15)
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; CHECK-NEXT: larl %r1, .LCPI0_1
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; CHECK-NEXT: stg %r0, 192(%r15)
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; CHECK-NEXT: vst %v0, 176(%r15), 3
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; CHECK-NEXT: vl %v0, 0(%r1), 3
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; CHECK-NEXT: vst %v0, 160(%r15), 3
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; CHECK-NEXT: vgbm %v0, 0
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; CHECK-NEXT: la %r6, 216(%r15)
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; CHECK-NEXT: lghi %r2, 1
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; CHECK-NEXT: lghi %r3, 2
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; CHECK-NEXT: lghi %r4, 3
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; CHECK-NEXT: lghi %r5, 4
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; CHECK-NEXT: vst %v0, 200(%r15), 3
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; CHECK-NEXT: vst %v0, 216(%r15), 3
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; CHECK-NEXT: brasl %r14, bar@PLT
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; CHECK-NEXT: lmg %r6, %r15, 280(%r15)
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; CHECK-NEXT: br %r14
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call void @bar (i64 1, i64 2, i64 3, i64 4, i128 0,
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i64 5, i64 6, i64 7, i64 8, i128 0)
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ret void
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}
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