6d03f51f0c
- _Float16 is now accepted by Clang. - The half IR type is fully handled by the backend. - These values are passed in FP registers and converted to/from float around each operation. - Compiler-rt conversion functions are now built for s390x including the missing extendhfdf2 which was added. Fixes #50374
162 lines
5.4 KiB
LLVM
162 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 -verify-machineinstrs \
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; RUN: | FileCheck %s
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;
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; Some tests with comparisons and their uses involving 16-bit floating point.
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; fcmp half; select half
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define half @fun0(half %Arg0, half %Arg1) {
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; CHECK-LABEL: fun0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -176
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; CHECK-NEXT: .cfi_def_cfa_offset 336
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; CHECK-NEXT: std %f8, 168(%r15) # 8-byte Spill
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; CHECK-NEXT: std %f9, 160(%r15) # 8-byte Spill
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; CHECK-NEXT: .cfi_offset %f8, -168
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; CHECK-NEXT: .cfi_offset %f9, -176
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; CHECK-NEXT: ldr %f8, %f2
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; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT
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; CHECK-NEXT: ldr %f9, %f0
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; CHECK-NEXT: ldr %f0, %f8
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; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT
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; CHECK-NEXT: ltebr %f1, %f9
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; CHECK-NEXT: # kill: def $f0s killed $f0s def $v0
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; CHECK-NEXT: jl .LBB0_2
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: vgmf %v0, 2, 8
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; CHECK-NEXT: .LBB0_2: # %entry
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; CHECK-NEXT: # kill: def $f0s killed $f0s killed $v0
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; CHECK-NEXT: brasl %r14, __truncsfhf2@PLT
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; CHECK-NEXT: ld %f8, 168(%r15) # 8-byte Reload
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; CHECK-NEXT: ld %f9, 160(%r15) # 8-byte Reload
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; CHECK-NEXT: lmg %r14, %r15, 288(%r15)
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; CHECK-NEXT: br %r14
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entry:
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%cmp = fcmp olt half %Arg0, 0xH0000
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%cond = select i1 %cmp, half %Arg1, half 1.0
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ret half %cond
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}
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; fcmp half; select i32
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define i32 @fun1(half %Arg0, i32 %Arg1) {
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; CHECK-LABEL: fun1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
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; CHECK-NEXT: .cfi_offset %r13, -56
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -160
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; CHECK-NEXT: .cfi_def_cfa_offset 320
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; CHECK-NEXT: lr %r13, %r2
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; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT
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; CHECK-NEXT: ltebr %f0, %f0
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; CHECK-NEXT: lochinl %r13, 0
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; CHECK-NEXT: lr %r2, %r13
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; CHECK-NEXT: lmg %r13, %r15, 264(%r15)
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; CHECK-NEXT: br %r14
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entry:
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%cmp = fcmp olt half %Arg0, 0xH0000
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%cond = select i1 %cmp, i32 %Arg1, i32 0
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ret i32 %cond
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}
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; icmp i32; select half
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define half @fun2(i32 %Arg0, half %Arg1) {
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; CHECK-LABEL: fun2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
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; CHECK-NEXT: .cfi_offset %r13, -56
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -160
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; CHECK-NEXT: .cfi_def_cfa_offset 320
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; CHECK-NEXT: lr %r13, %r2
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; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT
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; CHECK-NEXT: # kill: def $f0s killed $f0s def $v0
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; CHECK-NEXT: cije %r13, 0, .LBB2_2
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: vgmf %v0, 2, 8
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; CHECK-NEXT: .LBB2_2: # %entry
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; CHECK-NEXT: # kill: def $f0s killed $f0s killed $v0
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; CHECK-NEXT: brasl %r14, __truncsfhf2@PLT
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; CHECK-NEXT: lmg %r13, %r15, 264(%r15)
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; CHECK-NEXT: br %r14
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entry:
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%cmp = icmp eq i32 %Arg0, 0
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%cond = select i1 %cmp, half %Arg1, half 1.0
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ret half %cond
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}
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define i64 @fun3(i64 %a, i64 %b, half %f1, half %f2) #0 {
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; CHECK-LABEL: fun3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: stmg %r12, %r15, 96(%r15)
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; CHECK-NEXT: .cfi_offset %r12, -64
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; CHECK-NEXT: .cfi_offset %r13, -56
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -176
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; CHECK-NEXT: .cfi_def_cfa_offset 336
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; CHECK-NEXT: std %f8, 168(%r15) # 8-byte Spill
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; CHECK-NEXT: std %f9, 160(%r15) # 8-byte Spill
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; CHECK-NEXT: .cfi_offset %f8, -168
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; CHECK-NEXT: .cfi_offset %f9, -176
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; CHECK-NEXT: ldr %f8, %f0
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; CHECK-NEXT: ldr %f0, %f2
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; CHECK-NEXT: lgr %r13, %r3
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; CHECK-NEXT: lgr %r12, %r2
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; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT
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; CHECK-NEXT: ldr %f9, %f0
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; CHECK-NEXT: ldr %f0, %f8
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; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT
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; CHECK-NEXT: cebr %f0, %f9
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; CHECK-NEXT: ld %f8, 168(%r15) # 8-byte Reload
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; CHECK-NEXT: ld %f9, 160(%r15) # 8-byte Reload
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; CHECK-NEXT: selgre %r2, %r12, %r13
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; CHECK-NEXT: lmg %r12, %r15, 272(%r15)
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; CHECK-NEXT: br %r14
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%cond = call i1 @llvm.experimental.constrained.fcmp.f32(
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half %f1, half %f2,
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metadata !"oeq",
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metadata !"fpexcept.strict") #0
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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define half @fun4(half %Arg0, ptr %Dst) {
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; CHECK-LABEL: fun4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
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; CHECK-NEXT: .cfi_offset %r13, -56
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; CHECK-NEXT: .cfi_offset %r14, -48
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; CHECK-NEXT: .cfi_offset %r15, -40
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; CHECK-NEXT: aghi %r15, -160
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; CHECK-NEXT: .cfi_def_cfa_offset 320
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; CHECK-NEXT: lgr %r13, %r2
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; CHECK-NEXT: brasl %r14, __extendhfsf2@PLT
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; CHECK-NEXT: ltebr %f0, %f0
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; CHECK-NEXT: je .LBB4_2
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; CHECK-NEXT: # %bb.1: # %store
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; CHECK-NEXT: lzer %f0
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; CHECK-NEXT: vsteh %v0, 0(%r13), 0
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; CHECK-NEXT: .LBB4_2: # %exit
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; CHECK-NEXT: lzer %f0
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; CHECK-NEXT: lmg %r13, %r15, 264(%r15)
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; CHECK-NEXT: br %r14
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entry:
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%cmp = fcmp oeq half %Arg0, 0.0
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br i1 %cmp, label %exit, label %store
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store:
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store half 0.0, ptr %Dst
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br label %exit
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exit:
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ret half 0.0
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}
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declare i1 @llvm.experimental.constrained.fcmp.f32(half, half, metadata, metadata)
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