a65ccc1b9f
On processors supporting vector registers and SIMD instructions, enable i128 as legal type in VRs. This allows many operations to be implemented via native instructions directly in VRs (including add, subtract, logical operations and shifts). For a few other operations (e.g. multiply and divide, as well as atomic operations), we need to move the i128 value back to a GPR pair to use the corresponding instruction there. Overall, this is still beneficial. The patch includes the following LLVM changes: - Enable i128 as legal type - Set up legal operations (in SystemZInstrVector.td) - Custom expansion for i128 add/subtract with carry - Custom expansion for i128 comparisons and selects - Support for moving i128 to/from GPR pairs when required - Handle 128-bit integer constant values everywhere - Use i128 as intrinsic operand type where appropriate - Updated and new test cases In addition, clang builtins are updated to reflect the intrinsic operand type changes (which also improves compatibility with GCC).
157 lines
4.4 KiB
LLVM
157 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; Test 128-bit shift right logica in vector registers on z13
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Shift right logical immediate (general case).
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define i128 @f1(i128 %a) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepib %v1, 100
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; CHECK-NEXT: vsrlb %v0, %v0, %v1
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; CHECK-NEXT: vsrl %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = lshr i128 %a, 100
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ret i128 %res
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}
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; Shift right logical immediate (< 8 bits).
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define i128 @f2(i128 %a) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepib %v1, 7
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; CHECK-NEXT: vsrl %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = lshr i128 %a, 7
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ret i128 %res
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}
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; Shift right logical immediate (full bytes).
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define i128 @f3(i128 %a) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepib %v1, 32
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; CHECK-NEXT: vsrlb %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = lshr i128 %a, 32
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ret i128 %res
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}
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; Shift right logical variable.
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define i128 @f4(i128 %a, i128 %sh) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: l %r0, 12(%r4)
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; CHECK-NEXT: vlvgp %v1, %r0, %r0
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vsrlb %v0, %v0, %v1
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; CHECK-NEXT: vsrl %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = lshr i128 %a, %sh
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ret i128 %res
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}
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; Test removal of AND mask with only bottom 7 bits set.
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define i128 @f5(i128 %a, i128 %sh) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: l %r0, 12(%r4)
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; CHECK-NEXT: vlvgp %v1, %r0, %r0
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vsrlb %v0, %v0, %v1
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; CHECK-NEXT: vsrl %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%and = and i128 %sh, 127
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%shift = lshr i128 %a, %and
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ret i128 %shift
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}
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; Test removal of AND mask including but not limited to bottom 7 bits.
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define i128 @f6(i128 %a, i128 %sh) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: l %r0, 12(%r4)
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; CHECK-NEXT: vlvgp %v1, %r0, %r0
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vsrlb %v0, %v0, %v1
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; CHECK-NEXT: vsrl %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%and = and i128 %sh, 511
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%shift = lshr i128 %a, %and
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ret i128 %shift
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}
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; Test that AND is not removed when some lower 7 bits are not set.
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define i128 @f7(i128 %a, i128 %sh) {
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; CHECK-LABEL: f7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lhi %r0, 63
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; CHECK-NEXT: n %r0, 12(%r4)
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; CHECK-NEXT: vlvgp %v1, %r0, %r0
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vsrlb %v0, %v0, %v1
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; CHECK-NEXT: vsrl %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%and = and i128 %sh, 63
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%shift = lshr i128 %a, %and
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ret i128 %shift
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}
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; Test that AND with two register operands is not affected.
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define i128 @f8(i128 %a, i128 %b, i128 %sh) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v1, 0(%r4), 3
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; CHECK-NEXT: vl %v2, 0(%r5), 3
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; CHECK-NEXT: vn %v1, %v2, %v1
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; CHECK-NEXT: vlgvf %r0, %v1, 3
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; CHECK-NEXT: vlvgp %v1, %r0, %r0
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v1, %v1, 15
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; CHECK-NEXT: vsrlb %v0, %v0, %v1
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; CHECK-NEXT: vsrl %v0, %v0, %v1
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%and = and i128 %sh, %b
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%shift = lshr i128 %a, %and
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ret i128 %shift
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}
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; Test that AND is not entirely removed if the result is reused.
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define i128 @f9(i128 %a, i128 %sh) {
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; CHECK-LABEL: f9:
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; CHECK: # %bb.0:
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; CHECK-NEXT: larl %r1, .LCPI8_0
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; CHECK-NEXT: vl %v1, 0(%r4), 3
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; CHECK-NEXT: vl %v2, 0(%r1), 3
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; CHECK-NEXT: vn %v1, %v1, %v2
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; CHECK-NEXT: vlgvf %r0, %v1, 3
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; CHECK-NEXT: vlvgp %v2, %r0, %r0
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vrepb %v2, %v2, 15
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; CHECK-NEXT: vsrlb %v0, %v0, %v2
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; CHECK-NEXT: vsrl %v0, %v0, %v2
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; CHECK-NEXT: vaq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%and = and i128 %sh, 127
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%shift = lshr i128 %a, %and
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%reuse = add i128 %and, %shift
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ret i128 %reuse
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}
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