440c4b705a
Previous we used sra (X, size(X)-1); xor (add (X, Y), Y). By placing sub at the end, we allow RISCV to combine sign_extend_inreg with it to form subw. Some X86 tests for Z - abs(X) seem to have improved as well. Other targets look to be a wash. I had to modify ARM's abs matching code to match from sub instead of xor. Maybe instead ISD::ABS should be made legal. I'll try that in parallel to this patch. This is an alternative to D119099 which was focused on RISCV only. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D119171
56 lines
1.8 KiB
LLVM
56 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumb-eabi %s -verify-machineinstrs -o - | FileCheck %s --check-prefix=THUMB
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; RUN: llc -mtriple=thumbv6-eabi %s -verify-machineinstrs -o - | FileCheck %s --check-prefix=THUMBV6
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; The scheduler used to ignore OptionalDefs, and could unwittingly insert
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; a flag-setting instruction in between an ADDS and the corresponding ADC.
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; FIXME: The ABS lowering changed to XOR followed by SUB so this may no longer
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; be testing what it used to.
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define i1 @test(i64 %arg) {
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; THUMB-LABEL: test:
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; THUMB: @ %bb.0: @ %entry
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; THUMB-NEXT: .save {r4, lr}
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; THUMB-NEXT: push {r4, lr}
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; THUMB-NEXT: asrs r2, r1, #31
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; THUMB-NEXT: movs r3, r1
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; THUMB-NEXT: eors r3, r2
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; THUMB-NEXT: movs r4, r0
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; THUMB-NEXT: eors r4, r2
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; THUMB-NEXT: subs r4, r4, r2
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; THUMB-NEXT: sbcs r3, r2
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; THUMB-NEXT: eors r3, r1
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; THUMB-NEXT: eors r0, r4
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; THUMB-NEXT: orrs r0, r3
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; THUMB-NEXT: rsbs r1, r0, #0
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; THUMB-NEXT: adcs r0, r1
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; THUMB-NEXT: pop {r4}
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; THUMB-NEXT: pop {r1}
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; THUMB-NEXT: bx r1
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;
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; THUMBV6-LABEL: test:
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; THUMBV6: @ %bb.0: @ %entry
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; THUMBV6-NEXT: .save {r4, lr}
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; THUMBV6-NEXT: push {r4, lr}
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; THUMBV6-NEXT: asrs r2, r1, #31
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; THUMBV6-NEXT: mov r3, r1
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; THUMBV6-NEXT: eors r3, r2
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; THUMBV6-NEXT: mov r4, r0
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; THUMBV6-NEXT: eors r4, r2
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; THUMBV6-NEXT: subs r4, r4, r2
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; THUMBV6-NEXT: sbcs r3, r2
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; THUMBV6-NEXT: eors r3, r1
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; THUMBV6-NEXT: eors r0, r4
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; THUMBV6-NEXT: orrs r0, r3
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; THUMBV6-NEXT: rsbs r1, r0, #0
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; THUMBV6-NEXT: adcs r0, r1
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; THUMBV6-NEXT: pop {r4, pc}
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entry:
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%ispos = icmp sgt i64 %arg, -1
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%neg = sub i64 0, %arg
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%sel = select i1 %ispos, i64 %arg, i64 %neg
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%cmp2 = icmp eq i64 %sel, %arg
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ret i1 %cmp2
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}
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