e0ed0333f0
Re-landing #116970 after fixing miscompilation error. The original change made it possible for CMPZ to have multiple uses; `ARMDAGToDAGISel::SelectCMPZ` was not prepared for this. Pull Request: https://github.com/llvm/llvm-project/pull/118887 Original commit message: Following #116547 and #116676, this PR changes the type of results and operands of some nodes to accept / return a normal type instead of Glue. Unfortunately, changing the result type of one node requires changing the operand types of all potential consumer nodes, which in turn requires changing the result types of all other possible producer nodes. So this is a bulk change.
95 lines
4.5 KiB
LLVM
95 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs -tail-predication=enabled -o - %s | FileCheck %s
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%struct.SpeexPreprocessState_ = type { i32, i32, ptr, ptr }
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define void @foo(ptr nocapture readonly %st, ptr %x) {
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; CHECK-LABEL: foo:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, lr}
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: ldrd r12, r3, [r0]
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; CHECK-NEXT: ldrd r4, r2, [r0, #8]
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; CHECK-NEXT: rsb r12, r12, r3, lsl #1
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; CHECK-NEXT: dlstp.16 lr, r12
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; CHECK-NEXT: .LBB0_1: @ %do.body
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrh.u16 q0, [r2], #16
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; CHECK-NEXT: vstrh.16 q0, [r4], #16
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; CHECK-NEXT: letp lr, .LBB0_1
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; CHECK-NEXT: @ %bb.2: @ %do.end
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; CHECK-NEXT: ldr r3, [r0]
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; CHECK-NEXT: ldr r0, [r0, #8]
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; CHECK-NEXT: add.w r0, r0, r12, lsl #1
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; CHECK-NEXT: mov.w r2, #6144
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; CHECK-NEXT: dlstp.16 lr, r3
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; CHECK-NEXT: .LBB0_3: @ %do.body6
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; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: vldrh.u16 q0, [r1], #16
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; CHECK-NEXT: vcvt.f16.s16 q0, q0
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; CHECK-NEXT: vmul.f16 q0, q0, r2
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; CHECK-NEXT: vstrh.16 q0, [r0], #16
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; CHECK-NEXT: letp lr, .LBB0_3
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; CHECK-NEXT: @ %bb.4: @ %do.end13
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; CHECK-NEXT: pop {r4, pc}
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entry:
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%ps_size = getelementptr inbounds %struct.SpeexPreprocessState_, ptr %st, i32 0, i32 1
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%0 = load i32, ptr %ps_size, align 4
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%mul = shl nsw i32 %0, 1
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%1 = load i32, ptr %st, align 4
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%sub = sub nsw i32 %mul, %1
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%inbuf = getelementptr inbounds %struct.SpeexPreprocessState_, ptr %st, i32 0, i32 3
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%2 = load ptr, ptr %inbuf, align 4
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%frame = getelementptr inbounds %struct.SpeexPreprocessState_, ptr %st, i32 0, i32 2
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%3 = load ptr, ptr %frame, align 4
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br label %do.body
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do.body: ; preds = %do.body, %entry
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%pinbuff16.0 = phi ptr [ %2, %entry ], [ %add.ptr, %do.body ]
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%blkCnt.0 = phi i32 [ %sub, %entry ], [ %sub2, %do.body ]
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%pframef16.0 = phi ptr [ %3, %entry ], [ %add.ptr1, %do.body ]
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%4 = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %blkCnt.0)
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%5 = tail call fast <8 x half> @llvm.masked.load.v8f16.p0(ptr %pinbuff16.0, i32 2, <8 x i1> %4, <8 x half> zeroinitializer)
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tail call void @llvm.masked.store.v8f16.p0(<8 x half> %5, ptr %pframef16.0, i32 2, <8 x i1> %4)
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%add.ptr = getelementptr inbounds half, ptr %pinbuff16.0, i32 8
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%add.ptr1 = getelementptr inbounds half, ptr %pframef16.0, i32 8
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%sub2 = add nsw i32 %blkCnt.0, -8
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%cmp = icmp sgt i32 %blkCnt.0, 8
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br i1 %cmp, label %do.body, label %do.end
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do.end: ; preds = %do.body
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%6 = load ptr, ptr %frame, align 4
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%add.ptr4 = getelementptr inbounds half, ptr %6, i32 %sub
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%7 = load i32, ptr %st, align 4
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br label %do.body6
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do.body6: ; preds = %do.body6, %do.end
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%px.0 = phi ptr [ %x, %do.end ], [ %add.ptr8, %do.body6 ]
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%blkCnt.1 = phi i32 [ %7, %do.end ], [ %sub10, %do.body6 ]
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%pframef16.1 = phi ptr [ %add.ptr4, %do.end ], [ %add.ptr9, %do.body6 ]
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%8 = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %blkCnt.1)
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%9 = tail call <8 x i16> @llvm.masked.load.v8i16.p0(ptr %px.0, i32 2, <8 x i1> %8, <8 x i16> zeroinitializer)
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%10 = tail call fast <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16> %9, i32 0, <8 x i1> %8, <8 x half> undef)
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%11 = tail call fast <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %10, <8 x half> <half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800, half 0xH1800>, <8 x i1> %8, <8 x half> undef)
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tail call void @llvm.masked.store.v8f16.p0(<8 x half> %11, ptr %pframef16.1, i32 2, <8 x i1> %8)
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%add.ptr8 = getelementptr inbounds i16, ptr %px.0, i32 8
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%add.ptr9 = getelementptr inbounds half, ptr %pframef16.1, i32 8
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%sub10 = add nsw i32 %blkCnt.1, -8
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%cmp12 = icmp sgt i32 %blkCnt.1, 8
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br i1 %cmp12, label %do.body6, label %do.end13
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do.end13: ; preds = %do.body6
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ret void
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}
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declare <8 x i1> @llvm.arm.mve.vctp16(i32)
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declare <8 x half> @llvm.masked.load.v8f16.p0(ptr, i32 immarg, <8 x i1>, <8 x half>)
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declare void @llvm.masked.store.v8f16.p0(<8 x half>, ptr, i32 immarg, <8 x i1>)
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declare <8 x i16> @llvm.masked.load.v8i16.p0(ptr, i32 immarg, <8 x i1>, <8 x i16>)
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declare <8 x half> @llvm.arm.mve.vcvt.fp.int.predicated.v8f16.v8i16.v8i1(<8 x i16>, i32, <8 x i1>, <8 x half>)
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declare <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>)
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