2b78303e3f
Just like for regular IR we need to treat SELECT as conditionally blocking poison in SelectionDAG. So (unless the condition itself is poison) the result is only poison if the selected true/false value is poison. Thus, when doing DAG combines that turn SELECT into arithmetic/logical operations (e.g. AND/OR) we need to make sure that the new operations aren't more poisonous. One way to do that is to use FREEZE to make sure the operands aren't posion. This patch aims at fixing the kind of miscompiles reported in https://github.com/llvm/llvm-project/issues/84653 and https://github.com/llvm/llvm-project/issues/85190 Solution is to make sure that we insert FREEZE, if needed to make the fold sound, when using the foldBoolSelectToLogic and foldVSelectToSignBitSplatMask DAG combines.
297 lines
7.4 KiB
LLVM
297 lines
7.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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; RUN: llc < %s -mtriple=ve-unknown-unknown -enable-no-signed-zeros-fp-math \
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; RUN: -enable-no-nans-fp-math | FileCheck %s -check-prefix=OPT
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define double @maxf64(double, double) {
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; CHECK-LABEL: maxf64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.d %s2, %s0, %s1
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; CHECK-NEXT: cmov.d.gt %s1, %s0, %s2
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: maxf64:
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; OPT: # %bb.0:
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; OPT-NEXT: fmax.d %s0, %s0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = fcmp ogt double %0, %1
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%4 = select i1 %3, double %0, double %1
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ret double %4
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}
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define double @max2f64(double, double) {
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; CHECK-LABEL: max2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.d %s2, %s0, %s1
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; CHECK-NEXT: cmov.d.ge %s1, %s0, %s2
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: max2f64:
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; OPT: # %bb.0:
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; OPT-NEXT: fmax.d %s0, %s0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = fcmp oge double %0, %1
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%4 = select i1 %3, double %0, double %1
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ret double %4
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}
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; VE has no max for unordered comparison
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define double @maxuf64(double, double) {
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; CHECK-LABEL: maxuf64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.d %s2, %s0, %s1
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; CHECK-NEXT: cmov.d.gtnan %s1, %s0, %s2
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: maxuf64:
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; OPT: # %bb.0:
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; OPT-NEXT: fmax.d %s0, %s0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = fcmp ugt double %0, %1
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%4 = select i1 %3, double %0, double %1
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ret double %4
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}
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; VE has no max for unordered comparison
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define double @max2uf64(double, double) {
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; CHECK-LABEL: max2uf64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.d %s2, %s0, %s1
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; CHECK-NEXT: cmov.d.genan %s1, %s0, %s2
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: max2uf64:
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; OPT: # %bb.0:
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; OPT-NEXT: fmax.d %s0, %s0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = fcmp uge double %0, %1
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%4 = select i1 %3, double %0, double %1
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ret double %4
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}
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define float @maxf32(float, float) {
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; CHECK-LABEL: maxf32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s2, %s0, %s1
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; CHECK-NEXT: cmov.s.gt %s1, %s0, %s2
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: maxf32:
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; OPT: # %bb.0:
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; OPT-NEXT: fmax.s %s0, %s0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = fcmp ogt float %0, %1
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%4 = select i1 %3, float %0, float %1
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ret float %4
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}
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define float @max2f32(float, float) {
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; CHECK-LABEL: max2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s2, %s0, %s1
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; CHECK-NEXT: cmov.s.ge %s1, %s0, %s2
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: max2f32:
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; OPT: # %bb.0:
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; OPT-NEXT: fmax.s %s0, %s0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = fcmp oge float %0, %1
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%4 = select i1 %3, float %0, float %1
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ret float %4
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}
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define float @maxuf32(float, float) {
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; CHECK-LABEL: maxuf32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s2, %s0, %s1
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; CHECK-NEXT: cmov.s.gtnan %s1, %s0, %s2
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: maxuf32:
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; OPT: # %bb.0:
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; OPT-NEXT: fmax.s %s0, %s0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = fcmp ugt float %0, %1
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%4 = select i1 %3, float %0, float %1
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ret float %4
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}
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define float @max2uf32(float, float) {
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; CHECK-LABEL: max2uf32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fcmp.s %s2, %s0, %s1
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; CHECK-NEXT: cmov.s.genan %s1, %s0, %s2
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: max2uf32:
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; OPT: # %bb.0:
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; OPT-NEXT: fmax.s %s0, %s0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = fcmp uge float %0, %1
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%4 = select i1 %3, float %0, float %1
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ret float %4
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}
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define i64 @maxi64(i64, i64) {
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; CHECK-LABEL: maxi64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: maxs.l %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: maxi64:
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; OPT: # %bb.0:
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; OPT-NEXT: maxs.l %s0, %s0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = icmp sgt i64 %0, %1
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%4 = select i1 %3, i64 %0, i64 %1
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ret i64 %4
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}
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define i64 @max2i64(i64, i64) {
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; CHECK-LABEL: max2i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: maxs.l %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: max2i64:
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; OPT: # %bb.0:
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; OPT-NEXT: maxs.l %s0, %s0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = icmp sge i64 %0, %1
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%4 = select i1 %3, i64 %0, i64 %1
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ret i64 %4
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}
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define i64 @maxu64(i64, i64) {
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; CHECK-LABEL: maxu64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpu.l %s2, %s0, %s1
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; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: maxu64:
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; OPT: # %bb.0:
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; OPT-NEXT: cmpu.l %s2, %s0, %s1
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; OPT-NEXT: cmov.l.gt %s1, %s0, %s2
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; OPT-NEXT: or %s0, 0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = icmp ugt i64 %0, %1
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%4 = select i1 %3, i64 %0, i64 %1
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ret i64 %4
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}
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define i64 @max2u64(i64, i64) {
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; CHECK-LABEL: max2u64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpu.l %s2, %s0, %s1
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; CHECK-NEXT: cmov.l.ge %s1, %s0, %s2
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: max2u64:
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; OPT: # %bb.0:
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; OPT-NEXT: cmpu.l %s2, %s0, %s1
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; OPT-NEXT: cmov.l.ge %s1, %s0, %s2
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; OPT-NEXT: or %s0, 0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = icmp uge i64 %0, %1
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%4 = select i1 %3, i64 %0, i64 %1
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ret i64 %4
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}
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define i32 @maxi32(i32, i32) {
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; CHECK-LABEL: maxi32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: maxi32:
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; OPT: # %bb.0:
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; OPT-NEXT: maxs.w.sx %s0, %s0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = icmp sgt i32 %0, %1
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%4 = select i1 %3, i32 %0, i32 %1
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ret i32 %4
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}
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define i32 @max2i32(i32, i32) {
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; CHECK-LABEL: max2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: max2i32:
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; OPT: # %bb.0:
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; OPT-NEXT: maxs.w.sx %s0, %s0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = icmp sge i32 %0, %1
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%4 = select i1 %3, i32 %0, i32 %1
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ret i32 %4
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}
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define i32 @maxu32(i32, i32) {
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; CHECK-LABEL: maxu32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpu.w %s2, %s0, %s1
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; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: maxu32:
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; OPT: # %bb.0:
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; OPT-NEXT: cmpu.w %s2, %s0, %s1
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; OPT-NEXT: cmov.w.gt %s1, %s0, %s2
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; OPT-NEXT: or %s0, 0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = icmp ugt i32 %0, %1
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%4 = select i1 %3, i32 %0, i32 %1
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ret i32 %4
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}
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define i32 @max2u32(i32, i32) {
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; CHECK-LABEL: max2u32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: cmpu.w %s2, %s0, %s1
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; CHECK-NEXT: cmov.w.ge %s1, %s0, %s2
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; CHECK-NEXT: or %s0, 0, %s1
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: max2u32:
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; OPT: # %bb.0:
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; OPT-NEXT: cmpu.w %s2, %s0, %s1
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; OPT-NEXT: cmov.w.ge %s1, %s0, %s2
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; OPT-NEXT: or %s0, 0, %s1
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; OPT-NEXT: b.l.t (, %s10)
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%3 = icmp uge i32 %0, %1
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%4 = select i1 %3, i32 %0, i32 %1
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ret i32 %4
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}
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define zeroext i1 @maxi1(i1 zeroext, i1 zeroext) {
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; CHECK-LABEL: maxi1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: or %s0, %s0, %s1
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; CHECK-NEXT: and %s0, 1, %s0
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; CHECK-NEXT: b.l.t (, %s10)
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;
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; OPT-LABEL: maxi1:
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; OPT: # %bb.0:
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; OPT-NEXT: or %s0, %s0, %s1
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; OPT-NEXT: and %s0, 1, %s0
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; OPT-NEXT: b.l.t (, %s10)
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%3 = xor i1 %1, true
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%4 = and i1 %3, %0
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%5 = select i1 %4, i1 %0, i1 %1
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ret i1 %5
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}
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