aefedb1707
Add andm, orm, xorm, eqvm, nndm, negm, pcvm, lzvm, and tovm intrinsic instructions, a few pseudo instructions to expand logical intrinsic using VM512, a mechnism to expand such pseudo instructions, and regression tests. Also, assign vector mask types and vector mask register classes correctly. This is required to use VM512 registers as function arguments. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D93093
34 lines
1.0 KiB
LLVM
34 lines
1.0 KiB
LLVM
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test equivalence vm intrinsic instructions
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;;;
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;;; Note:
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;;; We test EQVM*mm and EQVM*yy instructions.
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; Function Attrs: nounwind readnone
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define fastcc <256 x i1> @eqvm_mmm(<256 x i1> %0, <256 x i1> %1) {
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; CHECK-LABEL: eqvm_mmm:
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; CHECK: # %bb.0:
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; CHECK-NEXT: eqvm %vm1, %vm1, %vm2
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call <256 x i1> @llvm.ve.vl.eqvm.mmm(<256 x i1> %0, <256 x i1> %1)
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ret <256 x i1> %3
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}
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; Function Attrs: nounwind readnone
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declare <256 x i1> @llvm.ve.vl.eqvm.mmm(<256 x i1>, <256 x i1>)
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; Function Attrs: nounwind readnone
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define fastcc <512 x i1> @eqvm_MMM(<512 x i1> %0, <512 x i1> %1) {
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; CHECK-LABEL: eqvm_MMM:
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; CHECK: # %bb.0:
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; CHECK-NEXT: eqvm %vm2, %vm2, %vm4
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; CHECK-NEXT: eqvm %vm3, %vm3, %vm5
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; CHECK-NEXT: b.l.t (, %s10)
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%3 = tail call <512 x i1> @llvm.ve.vl.eqvm.MMM(<512 x i1> %0, <512 x i1> %1)
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ret <512 x i1> %3
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}
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; Function Attrs: nounwind readnone
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declare <512 x i1> @llvm.ve.vl.eqvm.MMM(<512 x i1>, <512 x i1>)
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