aefedb1707
Add andm, orm, xorm, eqvm, nndm, negm, pcvm, lzvm, and tovm intrinsic instructions, a few pseudo instructions to expand logical intrinsic using VM512, a mechnism to expand such pseudo instructions, and regression tests. Also, assign vector mask types and vector mask register classes correctly. This is required to use VM512 registers as function arguments. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D93093
22 lines
574 B
LLVM
22 lines
574 B
LLVM
; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
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;;; Test leading zero of vm intrinsic instructions
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;;;
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;;; Note:
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;;; We test LZVM*ml instruction.
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; Function Attrs: nounwind readnone
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define fastcc i64 @lzvm_sml(<256 x i1> %0) {
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; CHECK-LABEL: lzvm_sml:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lea %s0, 256
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; CHECK-NEXT: lvl %s0
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; CHECK-NEXT: lzvm %s0, %vm1
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; CHECK-NEXT: b.l.t (, %s10)
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%2 = tail call i64 @llvm.ve.vl.lzvm.sml(<256 x i1> %0, i32 256)
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ret i64 %2
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.ve.vl.lzvm.sml(<256 x i1>, i32)
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