f0dd12ec5c
The first attempt missed changing test files for tools (update_llc_test_checks.py). Original commit message: This implements the main suggested change from issue #56498. Using the shorter (non-extending) instruction with only -Oz ("minsize") rather than -Os ("optsize") is left as a possible follow-up. As noted in the bug report, the zero-extending load may have shorter latency/better throughput across a wide range of x86 micro-arches, and it avoids a potential false dependency. The cost is an extra instruction byte. This could cause perf ups and downs from secondary effects, but I don't think it is possible to account for those in advance, and that will likely also depend on exact micro-arch. This does bring LLVM x86 codegen more in line with existing gcc codegen, so if problems are exposed they are more likely to occur for both compilers. Differential Revision: https://reviews.llvm.org/D129775
32 lines
1.1 KiB
LLVM
32 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- | FileCheck %s
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; Don't accidentally add the offset twice for trailing bytes.
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%struct.S63 = type { [63 x i8] }
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@g1s63 = external dso_local global %struct.S63 ; <ptr> [#uses=1]
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declare void @test63(ptr byval(%struct.S63) align 4 ) nounwind
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define void @testit63_entry_2E_ce() nounwind {
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; CHECK-LABEL: testit63_entry_2E_ce:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pushl %edi
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: subl $64, %esp
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; CHECK-NEXT: movl $15, %ecx
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; CHECK-NEXT: movl %esp, %edi
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; CHECK-NEXT: movl $g1s63, %esi
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; CHECK-NEXT: rep;movsl (%esi), %es:(%edi)
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; CHECK-NEXT: movzbl g1s63+62, %eax
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; CHECK-NEXT: movb %al, {{[0-9]+}}(%esp)
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; CHECK-NEXT: movzwl g1s63+60, %eax
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; CHECK-NEXT: movw %ax, {{[0-9]+}}(%esp)
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; CHECK-NEXT: calll test63@PLT
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; CHECK-NEXT: addl $64, %esp
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: popl %edi
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; CHECK-NEXT: retl
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tail call void @test63(ptr byval(%struct.S63) align 4 @g1s63) nounwind
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ret void
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}
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