69a322fed1
There are a variety of cases where we want more control over the exact
instruction emitted. This commit creates a new pass to fixup
instructions after the DAG has been lowered. The pass is only meant to
replace instructions that are guranteed to be interchangable, not to
do analysis for special cases.
Handling these instruction changes in in X86ISelLowering of
X86ISelDAGToDAG isn't ideal, as its liable to either break existing
patterns that expected a certain instruction or generate infinite
loops.
As well, operating as the MachineInstruction level allows us to access
scheduling/code size information for making the decisions.
Currently only implements `{v}permilps` -> `{v}shufps/{v}shufd` but
more transforms can be added.
Differential Revision: https://reviews.llvm.org/D143787
78 lines
2.6 KiB
LLVM
78 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s
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; Check that we perform a scalar XOR on i32.
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define void @pull_bitcast(ptr %pA, ptr %pB) {
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; CHECK-LABEL: pull_bitcast:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rsi), %eax
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; CHECK-NEXT: xorl %eax, (%rdi)
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; CHECK-NEXT: retq
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%A = load <4 x i8>, ptr %pA
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%B = load <4 x i8>, ptr %pB
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%C = xor <4 x i8> %A, %B
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store <4 x i8> %C, ptr %pA
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ret void
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}
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define <4 x i32> @multi_use_swizzle(ptr %pA, ptr %pB) {
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; CHECK-LABEL: multi_use_swizzle:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovaps (%rdi), %xmm0
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; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],mem[1,2]
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; CHECK-NEXT: vshufps {{.*#+}} xmm1 = xmm0[1,3,2,2]
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; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[2,1,0,2]
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; CHECK-NEXT: vxorps %xmm0, %xmm1, %xmm0
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; CHECK-NEXT: retq
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%A = load <4 x i32>, ptr %pA
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%B = load <4 x i32>, ptr %pB
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%S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 6>
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%S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 2>
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%S2 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 2>
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%R = xor <4 x i32> %S1, %S2
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ret <4 x i32> %R
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}
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define <4 x i8> @pull_bitcast2(ptr %pA, ptr %pB, ptr %pC) {
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; CHECK-LABEL: pull_bitcast2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl (%rdi), %eax
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; CHECK-NEXT: movl %eax, (%rdx)
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; CHECK-NEXT: xorl (%rsi), %eax
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; CHECK-NEXT: vmovd %eax, %xmm0
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; CHECK-NEXT: movl %eax, (%rdi)
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; CHECK-NEXT: retq
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%A = load <4 x i8>, ptr %pA
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store <4 x i8> %A, ptr %pC
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%B = load <4 x i8>, ptr %pB
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%C = xor <4 x i8> %A, %B
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store <4 x i8> %C, ptr %pA
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ret <4 x i8> %C
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}
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define <4 x i32> @reverse_1(ptr %pA, ptr %pB) {
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; CHECK-LABEL: reverse_1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmovaps (%rdi), %xmm0
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; CHECK-NEXT: retq
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%A = load <4 x i32>, ptr %pA
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%B = load <4 x i32>, ptr %pB
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%S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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%S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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ret <4 x i32> %S1
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}
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define <4 x i32> @no_reverse_shuff(ptr %pA, ptr %pB) {
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; CHECK-LABEL: no_reverse_shuff:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpermilps {{.*#+}} xmm0 = mem[2,3,2,3]
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; CHECK-NEXT: retq
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%A = load <4 x i32>, ptr %pA
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%B = load <4 x i32>, ptr %pB
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%S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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%S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
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ret <4 x i32> %S1
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}
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