1bc8b3258e
This pull request port `regallocfast` to new pass manager. It exposes the parameter `filter` to handle different register classes for AMDGPU. IIUC AMDGPU need to allocate different register classes separately so it need implement its own `--<reg-class>-regalloc`. Now users can use e.g. `-passe=regallocfast<filter=sgpr>` to allocate specific register class. The command line option `--regalloc-npm` is still in work progress, plan to reuse the syntax of passes, e.g. use `--regalloc-npm=regallocfast<filter=sgpr>,greedy<filter=vgpr>` to replace `--sgpr-regalloc` and `--vgpr-regalloc`.
33 lines
933 B
YAML
33 lines
933 B
YAML
# RUN: llc -mtriple=x86_64-- -run-pass=regallocfast -o - %s | FileCheck %s
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# RUN: llc -mtriple=x86_64-- -passes=regallocfast -o - %s | FileCheck %s
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...
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---
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name: foo
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alignment: 16
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vr128 }
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frameInfo:
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maxAlignment: 16
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stack:
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- { id: 0, size: 64, alignment: 16 }
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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; CHECK: renamable $xmm1 = V_SET0
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; CHECK-NEXT: renamable $xmm0 = V_SET0
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; CHECK-NEXT: renamable $xmm1 = PXORrr renamable $xmm1, renamable $xmm0
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; CHECK-NEXT: MOVAPSmr %stack.0, 1, $noreg, 0, $noreg, killed renamable $xmm1
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; CHECK-NEXT: MOVAPSmr %stack.0, 1, $noreg, 16, $noreg, killed renamable $xmm0
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%0:vr128 = V_SET0
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%1:vr128 = V_SET0
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%0:vr128 = PXORrr %0, %1
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MOVAPSmr %stack.0, 1, $noreg, 0, $noreg, %0
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MOVAPSmr %stack.0, 1, $noreg, 16, $noreg, %1
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JMP_1 %bb.0.entry
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RET 0
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...
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