e8245d5324
addr matching was the only gatekeeper for starting selecting G_LOAD and G_STORE using SDAG patterns. * Introduce a complex renderer gi_addr for addr. In this patch only the existing functionality has been implemented. The renderer's name is the same as in SDAG: selectAddr. Apparently the type of GIComplexOperandMatcher doesn't matter as RISCV also uses s32 for both 64 and 32 bit pointers. * X86SelectAddress now is used for both: pattern matching and manual selection. As a result it accumulates all the code that previously was distributed among different selection functions. * Replace getLoadStoreOp with getPtrLoadStoreOp in Load/Store selector as GlobalISel matcher or emitter can't map the pointer type into i32/i64 types used in SDAG patterns for pointers. So the load and store selection of pointers is still manual. getLoadStoreOp is still present because it is used in G_FCONSTANT lowering that requires extra efforts to select it using SDAG patterns. * Since truncating stores are not supported, we custom legalize them by matching types of store and MMO. * Introduce a constant pool flag in X86AddressMode because otherwise we need to introduce a GlobalISel copy for X86ISelAddressMode. * Also please notice in the tests that GlobalISel prefers to fold memory operands immediately comparing to SDAG. The reason is that GlobalISel doesn't have target hooks in GIM_CheckIsSafeToFold. Or maybe another check on profitability is required along with safety check that is currently not present.
130 lines
6.2 KiB
LLVM
130 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse,-sse2 %s -o - | FileCheck %s --check-prefixes SSE-X64
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; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse,-sse2 -fast-isel %s -o - | FileCheck %s --check-prefixes SSE-X64
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; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse,-sse2 -global-isel -global-isel-abort=1 %s -o - | FileCheck %s --check-prefixes SSE-X64-GISEL
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; RUN: llc -mtriple=i686-linux-gnu -mattr=+sse,-sse2 %s -o - | FileCheck %s --check-prefixes SSE-X86
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; RUN: llc -mtriple=i686-linux-gnu -mattr=+sse,-sse2 -fast-isel %s -o - | FileCheck %s --check-prefixes SSE-X86
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; RUN: llc -mtriple=i686-linux-gnu -mattr=+sse,-sse2 -global-isel -global-isel-abort=1 %s -o - | FileCheck %s --check-prefixes SSE-X86-GISEL
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define <8 x i32> @test_vector_v8i32() {
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; SSE-X64-LABEL: test_vector_v8i32:
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; SSE-X64: # %bb.0:
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; SSE-X64-NEXT: movq %rdi, %rax
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; SSE-X64-NEXT: movabsq $3043555126665690671, %rcx # imm = 0x2A3CE143233A3E2F
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; SSE-X64-NEXT: movq %rcx, 24(%rdi)
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; SSE-X64-NEXT: movabsq $-2720818644236378031, %rcx # imm = 0xDA3DB5DBCC07E051
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; SSE-X64-NEXT: movq %rcx, 16(%rdi)
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; SSE-X64-NEXT: movabsq $3043545045377446960, %rcx # imm = 0x2A3CD817E79F7430
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; SSE-X64-NEXT: movq %rcx, 8(%rdi)
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; SSE-X64-NEXT: movabsq $-2715530310134355376, %rcx # imm = 0xDA507F9207A2AA50
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; SSE-X64-NEXT: movq %rcx, (%rdi)
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; SSE-X64-NEXT: retq
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;
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; SSE-X64-GISEL-LABEL: test_vector_v8i32:
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; SSE-X64-GISEL: # %bb.0:
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; SSE-X64-GISEL-NEXT: movq %rdi, %rax
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; SSE-X64-GISEL-NEXT: movl $128100944, (%rdi) # imm = 0x7A2AA50
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; SSE-X64-GISEL-NEXT: movl $-632258670, 4(%rdi) # imm = 0xDA507F92
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; SSE-X64-GISEL-NEXT: movl $-408980432, 8(%rdi) # imm = 0xE79F7430
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; SSE-X64-GISEL-NEXT: movl $708630551, 12(%rdi) # imm = 0x2A3CD817
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; SSE-X64-GISEL-NEXT: movl $-871899055, 16(%rdi) # imm = 0xCC07E051
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; SSE-X64-GISEL-NEXT: movl $-633489957, 20(%rdi) # imm = 0xDA3DB5DB
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; SSE-X64-GISEL-NEXT: movl $591019567, 24(%rdi) # imm = 0x233A3E2F
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; SSE-X64-GISEL-NEXT: movl $708632899, 28(%rdi) # imm = 0x2A3CE143
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; SSE-X64-GISEL-NEXT: retq
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;
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; SSE-X86-LABEL: test_vector_v8i32:
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; SSE-X86: # %bb.0:
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; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; SSE-X86-NEXT: movl $708632899, 28(%eax) # imm = 0x2A3CE143
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; SSE-X86-NEXT: movl $591019567, 24(%eax) # imm = 0x233A3E2F
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; SSE-X86-NEXT: movl $-633489957, 20(%eax) # imm = 0xDA3DB5DB
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; SSE-X86-NEXT: movl $-871899055, 16(%eax) # imm = 0xCC07E051
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; SSE-X86-NEXT: movl $708630551, 12(%eax) # imm = 0x2A3CD817
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; SSE-X86-NEXT: movl $-408980432, 8(%eax) # imm = 0xE79F7430
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; SSE-X86-NEXT: movl $-632258670, 4(%eax) # imm = 0xDA507F92
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; SSE-X86-NEXT: movl $128100944, (%eax) # imm = 0x7A2AA50
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; SSE-X86-NEXT: retl $4
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;
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; SSE-X86-GISEL-LABEL: test_vector_v8i32:
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; SSE-X86-GISEL: # %bb.0:
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; SSE-X86-GISEL-NEXT: movl {{[0-9]+}}(%esp), %eax
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; SSE-X86-GISEL-NEXT: movl $128100944, (%eax) # imm = 0x7A2AA50
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; SSE-X86-GISEL-NEXT: movl $-632258670, 4(%eax) # imm = 0xDA507F92
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; SSE-X86-GISEL-NEXT: movl $-408980432, 8(%eax) # imm = 0xE79F7430
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; SSE-X86-GISEL-NEXT: movl $708630551, 12(%eax) # imm = 0x2A3CD817
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; SSE-X86-GISEL-NEXT: movl $-871899055, 16(%eax) # imm = 0xCC07E051
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; SSE-X86-GISEL-NEXT: movl $-633489957, 20(%eax) # imm = 0xDA3DB5DB
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; SSE-X86-GISEL-NEXT: movl $591019567, 24(%eax) # imm = 0x233A3E2F
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; SSE-X86-GISEL-NEXT: movl $708632899, 28(%eax) # imm = 0x2A3CE143
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; SSE-X86-GISEL-NEXT: retl
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ret <8 x i32> <i32 128100944, i32 3662708626, i32 3885986864, i32 708630551, i32 -871899055, i32 3661477339, i32 4885986863, i32 708632899>
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}
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define <4 x i32> @test_vector_v4i32() {
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; SSE-X64-LABEL: test_vector_v4i32:
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; SSE-X64: # %bb.0:
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; SSE-X64-NEXT: movq %rdi, %rax
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; SSE-X64-NEXT: movabsq $3043545045377446960, %rcx # imm = 0x2A3CD817E79F7430
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; SSE-X64-NEXT: movq %rcx, 8(%rdi)
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; SSE-X64-NEXT: movabsq $-2715530310134355376, %rcx # imm = 0xDA507F9207A2AA50
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; SSE-X64-NEXT: movq %rcx, (%rdi)
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; SSE-X64-NEXT: retq
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;
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; SSE-X64-GISEL-LABEL: test_vector_v4i32:
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; SSE-X64-GISEL: # %bb.0:
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; SSE-X64-GISEL-NEXT: movq %rdi, %rax
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; SSE-X64-GISEL-NEXT: movaps {{.*#+}} xmm0 = [128100944,3662708626,3885986864,708630551]
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; SSE-X64-GISEL-NEXT: movaps %xmm0, (%rdi)
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; SSE-X64-GISEL-NEXT: retq
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;
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; SSE-X86-LABEL: test_vector_v4i32:
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; SSE-X86: # %bb.0:
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; SSE-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; SSE-X86-NEXT: movl $708630551, 12(%eax) # imm = 0x2A3CD817
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; SSE-X86-NEXT: movl $-408980432, 8(%eax) # imm = 0xE79F7430
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; SSE-X86-NEXT: movl $-632258670, 4(%eax) # imm = 0xDA507F92
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; SSE-X86-NEXT: movl $128100944, (%eax) # imm = 0x7A2AA50
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; SSE-X86-NEXT: retl $4
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;
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; SSE-X86-GISEL-LABEL: test_vector_v4i32:
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; SSE-X86-GISEL: # %bb.0:
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; SSE-X86-GISEL-NEXT: movl {{[0-9]+}}(%esp), %eax
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; SSE-X86-GISEL-NEXT: movaps {{.*#+}} xmm0 = [128100944,3662708626,3885986864,708630551]
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; SSE-X86-GISEL-NEXT: movaps %xmm0, (%eax)
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; SSE-X86-GISEL-NEXT: retl
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ret <4 x i32> <i32 128100944, i32 3662708626, i32 3885986864, i32 708630551>
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}
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define <3 x i32> @test_vector_v3i32() {
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; SSE-X64-LABEL: test_vector_v3i32:
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; SSE-X64: # %bb.0:
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; SSE-X64-NEXT: movl $128100944, %eax # imm = 0x7A2AA50
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; SSE-X64-NEXT: movl $-632258670, %edx # imm = 0xDA507F92
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; SSE-X64-NEXT: movl $-408980432, %ecx # imm = 0xE79F7430
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; SSE-X64-NEXT: retq
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;
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; SSE-X64-GISEL-LABEL: test_vector_v3i32:
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; SSE-X64-GISEL: # %bb.0:
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; SSE-X64-GISEL-NEXT: movl $128100944, %eax # imm = 0x7A2AA50
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; SSE-X64-GISEL-NEXT: movl $-632258670, %edx # imm = 0xDA507F92
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; SSE-X64-GISEL-NEXT: movl $-408980432, %ecx # imm = 0xE79F7430
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; SSE-X64-GISEL-NEXT: retq
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;
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; SSE-X86-LABEL: test_vector_v3i32:
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; SSE-X86: # %bb.0:
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; SSE-X86-NEXT: movl $128100944, %eax # imm = 0x7A2AA50
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; SSE-X86-NEXT: movl $-632258670, %edx # imm = 0xDA507F92
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; SSE-X86-NEXT: movl $-408980432, %ecx # imm = 0xE79F7430
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; SSE-X86-NEXT: retl
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;
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; SSE-X86-GISEL-LABEL: test_vector_v3i32:
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; SSE-X86-GISEL: # %bb.0:
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; SSE-X86-GISEL-NEXT: movl $128100944, %eax # imm = 0x7A2AA50
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; SSE-X86-GISEL-NEXT: movl $-632258670, %edx # imm = 0xDA507F92
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; SSE-X86-GISEL-NEXT: movl $-408980432, %ecx # imm = 0xE79F7430
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; SSE-X86-GISEL-NEXT: retl
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ret <3 x i32> <i32 128100944, i32 3662708626, i32 3885986864>
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}
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