b7e4fba6e5
After #98505, the textual IR keyword `x86_mmx` was temporarily made to parse as `<1 x i64>`, so as not to require a lot of test update noise. This completes the removal of the type, by removing the`x86_mmx` keyword from the IR parser, and making the (now no-op) test updates via `sed -i 's/\bx86_mmx\b/<1 x i64>/g' $(git grep -l x86_mmx llvm/test/)`. Resulting bitcasts from <1 x i64> to itself were then manually deleted. Changes to llvm/test/Bitcode/compatibility-$VERSION.ll were reverted, as they're intended to be equivalent to the .bc file, if parsed by old LLVM, so shouldn't be updated. A few tests were removed, as they're no longer testing anything, in the following files: - llvm/test/Transforms/GlobalOpt/x86_mmx_load.ll - llvm/test/Transforms/InstCombine/cast.ll - llvm/test/Transforms/InstSimplify/ConstProp/gep-zeroinit-vector.ll Works towards issue #98272.
110 lines
3.2 KiB
LLVM
110 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse2 | FileCheck %s
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define i64 @t0(ptr %p) {
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; CHECK-LABEL: t0:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq (%rdi), %mm0
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; CHECK-NEXT: paddq %mm0, %mm0
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; CHECK-NEXT: movq %mm0, %rax
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; CHECK-NEXT: retq
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%t = load <1 x i64>, ptr %p
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%u = tail call <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64> %t, <1 x i64> %t)
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%s = bitcast <1 x i64> %u to i64
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ret i64 %s
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}
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define i64 @t1(ptr %p) {
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; CHECK-LABEL: t1:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq (%rdi), %mm0
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; CHECK-NEXT: paddd %mm0, %mm0
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; CHECK-NEXT: movq %mm0, %rax
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; CHECK-NEXT: retq
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%t = load <1 x i64>, ptr %p
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%u = tail call <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64> %t, <1 x i64> %t)
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%s = bitcast <1 x i64> %u to i64
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ret i64 %s
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}
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define i64 @t2(ptr %p) {
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; CHECK-LABEL: t2:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq (%rdi), %mm0
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; CHECK-NEXT: paddw %mm0, %mm0
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; CHECK-NEXT: movq %mm0, %rax
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; CHECK-NEXT: retq
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%t = load <1 x i64>, ptr %p
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%u = tail call <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64> %t, <1 x i64> %t)
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%s = bitcast <1 x i64> %u to i64
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ret i64 %s
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}
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define i64 @t3(ptr %p) {
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; CHECK-LABEL: t3:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq (%rdi), %mm0
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; CHECK-NEXT: paddb %mm0, %mm0
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; CHECK-NEXT: movq %mm0, %rax
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; CHECK-NEXT: retq
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%t = load <1 x i64>, ptr %p
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%u = tail call <1 x i64> @llvm.x86.mmx.padd.b(<1 x i64> %t, <1 x i64> %t)
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%s = bitcast <1 x i64> %u to i64
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ret i64 %s
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}
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@R = external global <1 x i64>
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define void @t4(<1 x i64> %A, <1 x i64> %B) {
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; CHECK-LABEL: t4:
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; CHECK: ## %bb.0: ## %entry
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; CHECK-NEXT: movq %rsi, %mm0
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; CHECK-NEXT: movq %rdi, %mm1
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; CHECK-NEXT: paddusw %mm0, %mm1
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; CHECK-NEXT: movq _R@GOTPCREL(%rip), %rax
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; CHECK-NEXT: movq %mm1, (%rax)
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; CHECK-NEXT: emms
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; CHECK-NEXT: retq
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entry:
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%tmp7 = tail call <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64> %A, <1 x i64> %B)
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store <1 x i64> %tmp7, ptr @R
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tail call void @llvm.x86.mmx.emms()
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ret void
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}
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define i64 @t5(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: t5:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movd %esi, %xmm0
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; CHECK-NEXT: movd %edi, %xmm1
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; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
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; CHECK-NEXT: movq %xmm1, %rax
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; CHECK-NEXT: retq
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%v0 = insertelement <2 x i32> undef, i32 %a, i32 0
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%v1 = insertelement <2 x i32> %v0, i32 %b, i32 1
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%conv = bitcast <2 x i32> %v1 to i64
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ret i64 %conv
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}
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declare <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64>, i32)
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define <1 x i64> @t6(i64 %t) {
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; CHECK-LABEL: t6:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq %rdi, %mm0
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; CHECK-NEXT: psllq $48, %mm0
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; CHECK-NEXT: movq %mm0, %rax
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; CHECK-NEXT: retq
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%t1 = insertelement <1 x i64> undef, i64 %t, i32 0
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%t2 = tail call <1 x i64> @llvm.x86.mmx.pslli.q(<1 x i64> %t1, i32 48)
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ret <1 x i64> %t2
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}
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declare <1 x i64> @llvm.x86.mmx.paddus.w(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.x86.mmx.padd.b(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.x86.mmx.padd.w(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.x86.mmx.padd.d(<1 x i64>, <1 x i64>)
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declare <1 x i64> @llvm.x86.mmx.padd.q(<1 x i64>, <1 x i64>)
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declare void @llvm.x86.mmx.emms()
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