f0dd12ec5c
The first attempt missed changing test files for tools (update_llc_test_checks.py). Original commit message: This implements the main suggested change from issue #56498. Using the shorter (non-extending) instruction with only -Oz ("minsize") rather than -Os ("optsize") is left as a possible follow-up. As noted in the bug report, the zero-extending load may have shorter latency/better throughput across a wide range of x86 micro-arches, and it avoids a potential false dependency. The cost is an extra instruction byte. This could cause perf ups and downs from secondary effects, but I don't think it is possible to account for those in advance, and that will likely also depend on exact micro-arch. This does bring LLVM x86 codegen more in line with existing gcc codegen, so if problems are exposed they are more likely to occur for both compilers. Differential Revision: https://reviews.llvm.org/D129775
149 lines
3.8 KiB
LLVM
149 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s --check-prefix=X32
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define i8 @select_i8_neg1_or_0(i1 %a) {
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; X64-LABEL: select_i8_neg1_or_0:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: andb $1, %al
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; X64-NEXT: negb %al
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i8_neg1_or_0:
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; X32: # %bb.0:
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: andb $1, %al
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; X32-NEXT: negb %al
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; X32-NEXT: retl
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%b = sext i1 %a to i8
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ret i8 %b
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}
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define i8 @select_i8_neg1_or_0_zeroext(i1 zeroext %a) {
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; X64-LABEL: select_i8_neg1_or_0_zeroext:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: negb %al
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i8_neg1_or_0_zeroext:
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; X32: # %bb.0:
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: negb %al
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; X32-NEXT: retl
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%b = sext i1 %a to i8
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ret i8 %b
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}
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define i16 @select_i16_neg1_or_0(i1 %a) {
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; X64-LABEL: select_i16_neg1_or_0:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: andl $1, %eax
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; X64-NEXT: negl %eax
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i16_neg1_or_0:
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; X32: # %bb.0:
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: andl $1, %eax
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; X32-NEXT: negl %eax
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; X32-NEXT: # kill: def $ax killed $ax killed $eax
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; X32-NEXT: retl
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%b = sext i1 %a to i16
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ret i16 %b
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}
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define i16 @select_i16_neg1_or_0_zeroext(i1 zeroext %a) {
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; X64-LABEL: select_i16_neg1_or_0_zeroext:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: negl %eax
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i16_neg1_or_0_zeroext:
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; X32: # %bb.0:
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: negl %eax
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; X32-NEXT: # kill: def $ax killed $ax killed $eax
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; X32-NEXT: retl
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%b = sext i1 %a to i16
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ret i16 %b
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}
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define i32 @select_i32_neg1_or_0(i1 %a) {
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; X64-LABEL: select_i32_neg1_or_0:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: andl $1, %eax
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; X64-NEXT: negl %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i32_neg1_or_0:
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; X32: # %bb.0:
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: andl $1, %eax
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; X32-NEXT: negl %eax
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; X32-NEXT: retl
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%b = sext i1 %a to i32
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ret i32 %b
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}
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define i32 @select_i32_neg1_or_0_zeroext(i1 zeroext %a) {
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; X64-LABEL: select_i32_neg1_or_0_zeroext:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: negl %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i32_neg1_or_0_zeroext:
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; X32: # %bb.0:
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: negl %eax
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; X32-NEXT: retl
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%b = sext i1 %a to i32
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ret i32 %b
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}
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define i64 @select_i64_neg1_or_0(i1 %a) {
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; X64-LABEL: select_i64_neg1_or_0:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: andl $1, %eax
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; X64-NEXT: negq %rax
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i64_neg1_or_0:
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; X32: # %bb.0:
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: andl $1, %eax
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; X32-NEXT: negl %eax
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; X32-NEXT: movl %eax, %edx
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; X32-NEXT: retl
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%b = sext i1 %a to i64
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ret i64 %b
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}
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define i64 @select_i64_neg1_or_0_zeroext(i1 zeroext %a) {
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; X64-LABEL: select_i64_neg1_or_0_zeroext:
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; X64: # %bb.0:
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: negq %rax
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; X64-NEXT: retq
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;
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; X32-LABEL: select_i64_neg1_or_0_zeroext:
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; X32: # %bb.0:
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: negl %eax
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; X32-NEXT: movl %eax, %edx
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; X32-NEXT: retl
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%b = sext i1 %a to i64
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ret i64 %b
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}
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