Yingwei Zheng 62735d26b1
[DAGCombine] Correctly extend the constant RHS in TargetLowering::SimplifySetCC (#152862)
In https://github.com/llvm/llvm-project/pull/150270, when the predicate
is eq/ne and the trunc has only an nsw flag, the RHS is incorrectly
zero-extended.

Closes https://github.com/llvm/llvm-project/issues/152630.
2025-08-10 01:24:37 +08:00

35 lines
912 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
define i32 @pr152630(i1 %cond) nounwind {
; CHECK-LABEL: pr152630:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andl $1, %edi
; CHECK-NEXT: decl %edi
; CHECK-NEXT: cmpl $-1, %edi
; CHECK-NEXT: je .LBB0_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: movzbl %dil, %eax
; CHECK-NEXT: testl %eax, %eax
; CHECK-NEXT: jne .LBB0_3
; CHECK-NEXT: .LBB0_2: # %if.then
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_3: # %if.else
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: retq
entry:
%sel = select i1 %cond, i32 0, i32 -1
%conv = trunc nsw i32 %sel to i8
switch i8 %conv, label %if.else [
i8 -1, label %if.then
i8 0, label %if.then
]
if.then:
ret i32 0
if.else:
ret i32 1
}