f0dd12ec5c
The first attempt missed changing test files for tools (update_llc_test_checks.py). Original commit message: This implements the main suggested change from issue #56498. Using the shorter (non-extending) instruction with only -Oz ("minsize") rather than -Os ("optsize") is left as a possible follow-up. As noted in the bug report, the zero-extending load may have shorter latency/better throughput across a wide range of x86 micro-arches, and it avoids a potential false dependency. The cost is an extra instruction byte. This could cause perf ups and downs from secondary effects, but I don't think it is possible to account for those in advance, and that will likely also depend on exact micro-arch. This does bring LLVM x86 codegen more in line with existing gcc codegen, so if problems are exposed they are more likely to occur for both compilers. Differential Revision: https://reviews.llvm.org/D129775
35 lines
1.1 KiB
LLVM
35 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-linux-gnu | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s --check-prefix=X64
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%destTy = type { i2, i2 }
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define void @crash(i64 %x0, i64 %y0, ptr nocapture %dest) nounwind {
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; X86-LABEL: crash:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: shlb $2, %dl
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; X86-NEXT: andb $3, %cl
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; X86-NEXT: orb %dl, %cl
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; X86-NEXT: andb $15, %cl
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; X86-NEXT: movb %cl, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: crash:
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; X64: # %bb.0:
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; X64-NEXT: shlb $2, %sil
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; X64-NEXT: andb $3, %dil
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; X64-NEXT: orb %sil, %dil
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; X64-NEXT: andb $15, %dil
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; X64-NEXT: movb %dil, (%rdx)
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; X64-NEXT: retq
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%x1 = trunc i64 %x0 to i2
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%y1 = trunc i64 %y0 to i2
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%1 = insertelement <2 x i2> undef, i2 %x1, i32 0
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%2 = insertelement <2 x i2> %1, i2 %y1, i32 1
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store <2 x i2> %2, ptr %dest, align 1
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ret void
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}
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