f0dd12ec5c
The first attempt missed changing test files for tools (update_llc_test_checks.py). Original commit message: This implements the main suggested change from issue #56498. Using the shorter (non-extending) instruction with only -Oz ("minsize") rather than -Os ("optsize") is left as a possible follow-up. As noted in the bug report, the zero-extending load may have shorter latency/better throughput across a wide range of x86 micro-arches, and it avoids a potential false dependency. The cost is an extra instruction byte. This could cause perf ups and downs from secondary effects, but I don't think it is possible to account for those in advance, and that will likely also depend on exact micro-arch. This does bring LLVM x86 codegen more in line with existing gcc codegen, so if problems are exposed they are more likely to occur for both compilers. Differential Revision: https://reviews.llvm.org/D129775
43 lines
1.2 KiB
LLVM
43 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown-linux-gnu | FileCheck %s
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@d = global i32 0, align 4
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; Verify the sar happens before ecx is clobbered with the parameter being
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; passed to fn3
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define i32 @fn4(i32 %i) #0 {
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; CHECK-LABEL: fn4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: subl $8, %esp
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movzbl d, %ecx
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; CHECK-NEXT: movl %eax, %esi
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; CHECK-NEXT: sarl %cl, %esi
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; CHECK-NEXT: subl $8, %esp
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; CHECK-NEXT: movl $2, %ecx
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; CHECK-NEXT: movl $5, %edx
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; CHECK-NEXT: pushl %eax
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; CHECK-NEXT: pushl %esi
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; CHECK-NEXT: calll fn3@PLT
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; CHECK-NEXT: addl $16, %esp
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testl %esi, %esi
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; CHECK-NEXT: setle %al
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; CHECK-NEXT: addl $8, %esp
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; CHECK-NEXT: popl %esi
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; CHECK-NEXT: retl
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entry:
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%0 = load i32, ptr @d, align 4
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%shr = ashr i32 %i, %0
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tail call fastcc void @fn3(i32 2, i32 5, i32 %shr, i32 %i)
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%cmp = icmp slt i32 %shr, 1
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%. = zext i1 %cmp to i32
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ret i32 %.
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}
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declare void @fn3(i32 %p1, i32 %p2, i32 %p3, i32 %p4) #0
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attributes #0 = { nounwind }
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