189900eb14
This stops reporting CostPerUse 1 for `R8`-`R15` and `XMM8`-`XMM31`.
This was previously done because instruction encoding require a REX
prefix when using them resulting in longer instruction encodings. I
found that this regresses the quality of the register allocation as the
costs impose an ordering on eviction candidates. I also feel that there
is a bit of an impedance mismatch as the actual costs occure when
encoding instructions using those registers, but the order of VReg
assignments is not primarily ordered by number of Defs+Uses.
I did extensive measurements with the llvm-test-suite wiht SPEC2006 +
SPEC2017 included, internal services showed similar patterns. Generally
there are a log of improvements but also a lot of regression. But on
average the allocation quality seems to improve at a small code size
regression.
Results for measuring static and dynamic instruction counts:
Dynamic Counts (scaled by execution frequency) / Optimization Remarks:
Spills+FoldedSpills -5.6%
Reloads+FoldedReloads -4.2%
Copies -0.1%
Static / LLVM Statistics:
regalloc.NumSpills mean -1.6%, geomean -2.8%
regalloc.NumReloads mean -1.7%, geomean -3.1%
size..text mean +0.4%, geomean +0.4%
Static / LLVM Statistics:
mean -2.2%, geomean -3.1%) regalloc.NumSpills
mean -2.6%, geomean -3.9%) regalloc.NumReloads
mean +0.6%, geomean +0.6%) size..text
Static / LLVM Statistics:
regalloc.NumSpills mean -3.0%
regalloc.NumReloads mean -3.3%
size..text mean +0.3%, geomean +0.3%
Differential Revision: https://reviews.llvm.org/D133902
140 lines
5.4 KiB
LLVM
140 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 -x86-asm-syntax=intel -mtriple=x86_64 -mcpu=skylake-avx512 < %s | FileCheck %s
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declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64, i64)
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declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64, i64)
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declare <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64, i64)
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declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64, i64)
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declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
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declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i32(i32, i32)
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define <7 x i1> @create_mask7(i64 %0) {
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; CHECK-LABEL: create_mask7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mov rax, rdi
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; CHECK-NEXT: vpbroadcastq zmm0, rsi
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; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: kshiftrb k1, k0, 6
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; CHECK-NEXT: kmovd ecx, k1
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; CHECK-NEXT: kshiftrb k1, k0, 5
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; CHECK-NEXT: kmovd edx, k1
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; CHECK-NEXT: kshiftrb k1, k0, 4
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; CHECK-NEXT: kmovd esi, k1
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; CHECK-NEXT: kshiftrb k1, k0, 3
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; CHECK-NEXT: kmovd edi, k1
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; CHECK-NEXT: kshiftrb k1, k0, 2
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; CHECK-NEXT: kmovd r8d, k1
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; CHECK-NEXT: kshiftrb k1, k0, 1
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; CHECK-NEXT: kmovd r9d, k1
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; CHECK-NEXT: kmovd r10d, k0
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; CHECK-NEXT: and r10b, 1
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; CHECK-NEXT: and r9b, 1
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; CHECK-NEXT: add r9b, r9b
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; CHECK-NEXT: or r9b, r10b
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; CHECK-NEXT: and r8b, 1
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; CHECK-NEXT: shl r8b, 2
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; CHECK-NEXT: or r8b, r9b
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; CHECK-NEXT: and dil, 1
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; CHECK-NEXT: shl dil, 3
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; CHECK-NEXT: or dil, r8b
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; CHECK-NEXT: and sil, 1
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; CHECK-NEXT: shl sil, 4
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; CHECK-NEXT: or sil, dil
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; CHECK-NEXT: and dl, 1
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; CHECK-NEXT: shl dl, 5
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; CHECK-NEXT: or dl, sil
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; CHECK-NEXT: shl cl, 6
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; CHECK-NEXT: or cl, dl
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; CHECK-NEXT: and cl, 127
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; CHECK-NEXT: mov byte ptr [rax], cl
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: ret
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%2 = call <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64 0, i64 %0)
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ret <7 x i1> %2
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}
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define <16 x i1> @create_mask16(i64 %0) {
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; CHECK-LABEL: create_mask16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpbroadcastq zmm0, rdi
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; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: kunpckbw k0, k1, k0
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; CHECK-NEXT: vpmovm2b xmm0, k0
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: ret
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%2 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 0, i64 %0)
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ret <16 x i1> %2
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}
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define <32 x i1> @create_mask32(i64 %0) {
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; CHECK-LABEL: create_mask32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpbroadcastq zmm0, rdi
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; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: kunpckbw k0, k1, k0
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; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: kunpckbw k1, k1, k2
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; CHECK-NEXT: kunpckwd k0, k1, k0
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; CHECK-NEXT: vpmovm2b ymm0, k0
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; CHECK-NEXT: ret
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%2 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 0, i64 %0)
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ret <32 x i1> %2
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}
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define <64 x i1> @create_mask64(i64 %0) {
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; CHECK-LABEL: create_mask64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpbroadcastq zmm0, rdi
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; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: kunpckbw k0, k1, k0
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; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: kunpckbw k1, k1, k2
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; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: kunpckwd k0, k1, k0
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; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: kunpckbw k1, k1, k2
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; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: vpcmpnleuq k3, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: kunpckbw k2, k3, k2
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; CHECK-NEXT: kunpckwd k1, k2, k1
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; CHECK-NEXT: kunpckdq k0, k1, k0
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; CHECK-NEXT: vpmovm2b zmm0, k0
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; CHECK-NEXT: ret
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%2 = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 0, i64 %0)
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ret <64 x i1> %2
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}
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define <16 x i1> @create_mask16_i32(i32 %0) {
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; CHECK-LABEL: create_mask16_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpbroadcastd zmm0, edi
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; CHECK-NEXT: vpcmpnleud k0, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: vpmovm2b xmm0, k0
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: ret
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%2 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 %0)
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ret <16 x i1> %2
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}
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define <64 x i1> @create_mask64_i32(i32 %0) {
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; CHECK-LABEL: create_mask64_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpbroadcastd zmm0, edi
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; CHECK-NEXT: vpcmpnleud k0, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: vpcmpnleud k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: vpcmpnleud k2, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: kunpckwd k0, k1, k0
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; CHECK-NEXT: vpcmpnleud k1, zmm0, zmmword ptr [rip + {{\.?LCPI[0-9]+_[0-9]+}}]
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; CHECK-NEXT: kunpckwd k1, k1, k2
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; CHECK-NEXT: kunpckdq k0, k1, k0
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; CHECK-NEXT: vpmovm2b zmm0, k0
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; CHECK-NEXT: ret
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%2 = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i32(i32 0, i32 %0)
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ret <64 x i1> %2
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}
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