b22fa9093b
Add KnownBits computations to ValueTracking and X86 DAG lowering.
These instructions add/subtract adjacent vector elements in their operands. Example: phadd [X1, X2] [Y1, Y2] = [X1 + X2, Y1 + Y2]. This means that, in this example, we can compute the KnownBits of the operation by computing the KnownBits of [X1, X2] + [X1, X2] and [Y1, Y2] + [Y1, Y2] and intersecting the results. This approach also generalizes to all x86 vector types.
There are also the operations phadd.sw and phsub.sw, which perform saturating addition/subtraction. Use sadd_sat and ssub_sat to compute the KnownBits of these operations.
Also adjust the existing test case pr53247.ll because it can be transformed to a constant using the new KnownBits computation.
Fixes #82516.
22 lines
832 B
LLVM
22 lines
832 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSE
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX
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define i32 @PR53247(){
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; SSE-LABEL: PR53247:
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; SSE: # %bb.0: # %entry
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; SSE-NEXT: xorl %eax, %eax
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; SSE-NEXT: retq
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;
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; AVX-LABEL: PR53247:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: xorl %eax, %eax
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; AVX-NEXT: retq
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entry:
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%0 = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> zeroinitializer, <4 x i32> zeroinitializer)
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%1 = call <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32> %0, <4 x i32> zeroinitializer)
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%vecext.i = extractelement <4 x i32> %1, i32 0
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ret i32 %vecext.i
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}
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declare <4 x i32> @llvm.x86.ssse3.phadd.d.128(<4 x i32>, <4 x i32>)
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