02ba5b8c6b
No longer conservatively assume a load/store accesses the stack when we can prove that we did not compute any stack-relative address up to this point in the program. We do this in a cheap not-quite-a-dataflow-analysis: Assume `NoStackAddressUsed` when all predecessors of a block already guarantee it. Process blocks in reverse post order to guarantee that except for loop headers we have processed all predecessors of a block before processing the block itself. For loops we accept the conservative answer as they are unlikely to be shrink-wrappable anyway. Differential Revision: https://reviews.llvm.org/D152213
65 lines
1.9 KiB
LLVM
65 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-linux-generic | FileCheck %s
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@e = global i16 0, align 2
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@a = global i32 0, align 4
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@c = global i32 0, align 4
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@b = global i64 0, align 8
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; Check the test instruction won't be optimizated by peephole opt.
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define dso_local i32 @main() nounwind {
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; CHECK-LABEL: main:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movq e@GOTPCREL(%rip), %rax
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; CHECK-NEXT: movw $1, (%rax)
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; CHECK-NEXT: movq b@GOTPCREL(%rip), %rax
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; CHECK-NEXT: movq $1, (%rax)
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; CHECK-NEXT: movq a@GOTPCREL(%rip), %rax
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; CHECK-NEXT: movl (%rax), %ecx
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; CHECK-NEXT: movl $-2, %eax
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; CHECK-NEXT: sarl %cl, %eax
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; CHECK-NEXT: movq c@GOTPCREL(%rip), %rdx
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; CHECK-NEXT: movl (%rdx), %edx
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; CHECK-NEXT: decl %edx
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; CHECK-NEXT: movzwl %ax, %eax
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; CHECK-NEXT: decl %eax
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; CHECK-NEXT: xorl %edx, %eax
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; CHECK-NEXT: notl %ecx
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; CHECK-NEXT: andl %eax, %ecx
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; CHECK-NEXT: testq %rcx, %rcx
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; CHECK-NEXT: jle .LBB0_2
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; CHECK-NEXT: # %bb.1: # %if.end
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB0_2: # %if.then
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: callq abort@PLT
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entry:
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store i16 1, ptr @e, align 2
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store i64 1, ptr @b, align 8
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%0 = load i32, ptr @a, align 4
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%shr = ashr i32 -2, %0
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%1 = load i32, ptr @c, align 4
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%sub = add i32 %1, -1
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%conv2 = zext i32 %sub to i64
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%2 = and i32 %shr, 65535
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%conv3 = zext i32 %2 to i64
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%sub4 = add nsw i64 %conv3, -1
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%xor = xor i64 %sub4, %conv2
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%neg5 = xor i32 %0, -1
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%conv6 = sext i32 %neg5 to i64
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%and = and i64 %xor, %conv6
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%cmp = icmp slt i64 %and, 1
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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call void @abort() #2
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unreachable
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if.end: ; preds = %entry
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ret i32 0
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}
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declare void @abort()
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