075202d126
This fixes [issue 62242](https://github.com/llvm/llvm-project/issues/62242) This code block can potentially swap the order of V1 and V2 in Ops and therefore also in the unpck instruction generated. ``` SDValue &Op = Ops[Elt & 1]; if (M < NumElts && (Op.isUndef() || Op == V1)) Op = V1; else if (NumElts <= M && (Op.isUndef() || Op == V2)) { Op = V2; NormM -= NumElts; } else return SDValue(); ``` But the permute mask is calculated assuming the first operand being V1 and second V2, therefore causing a mis-compile. First check if the input operands are swapped, and then calculate the permute mask based on that. Differential Revision: https://reviews.llvm.org/D148843
15 lines
740 B
LLVM
15 lines
740 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX2
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define <4 x i32> @unpck_permute_canonicalized_mask(<4 x i32> %a, <4 x i32> %b) {
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; AVX2-LABEL: unpck_permute_canonicalized_mask:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
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; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,3,2,1]
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; AVX2-NEXT: retq
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; This mask will get canonicalized to vector_shuffle<6, 3, -1, 2> %b, %a.
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; Make sure the generated permute masks are still correct.
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%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 7, i32 undef, i32 6>
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ret <4 x i32> %shuffle
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}
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