9540a7ae82
The dpbusd_const.ll test change is due to us losing the expanded add reduction pattern as one of the elements is known to be zero (removing one of the adds from the reduction pyramid). I don't think its of concern. Noticed while working on #107423
191 lines
9.5 KiB
LLVM
191 lines
9.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0
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declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #0
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define void @SHA256_Compress_Generic(ptr noundef %ctx) #1 {
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; CHECK-LABEL: SHA256_Compress_Generic:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movbel 0, %eax
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; CHECK-NEXT: movbel 12(%rdi), %ecx
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; CHECK-NEXT: vmovd %eax, %xmm0
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; CHECK-NEXT: vmovdqa {{.*#+}} xmm1 = [128,128,128,128,0,1,2,3,128,128,128,128,128,128,128,128]
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; CHECK-NEXT: vpshufb %xmm1, %xmm0, %xmm2
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; CHECK-NEXT: vpsrld $17, %xmm2, %xmm0
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; CHECK-NEXT: vpslld $15, %xmm2, %xmm3
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; CHECK-NEXT: vpor %xmm0, %xmm3, %xmm0
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; CHECK-NEXT: vpsrld $19, %xmm2, %xmm3
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; CHECK-NEXT: vpslld $13, %xmm2, %xmm4
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; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm3
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; CHECK-NEXT: vpxor %xmm3, %xmm0, %xmm3
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; CHECK-NEXT: vpxor %xmm2, %xmm3, %xmm0
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; CHECK-NEXT: vmovd %ecx, %xmm4
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; CHECK-NEXT: vpshufb %xmm1, %xmm4, %xmm1
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; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm1
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; CHECK-NEXT: vpsrld $17, %xmm1, %xmm0
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; CHECK-NEXT: vpslld $15, %xmm1, %xmm4
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; CHECK-NEXT: vpor %xmm0, %xmm4, %xmm0
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; CHECK-NEXT: vpsrld $19, %xmm1, %xmm4
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; CHECK-NEXT: vpslld $13, %xmm1, %xmm5
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; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm4
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; CHECK-NEXT: vpxor %xmm4, %xmm0, %xmm0
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; CHECK-NEXT: vpxor %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0
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; CHECK-NEXT: vpsrld $17, %xmm0, %xmm4
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; CHECK-NEXT: vpslld $15, %xmm0, %xmm5
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; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm4
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; CHECK-NEXT: vpsrld $19, %xmm0, %xmm5
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; CHECK-NEXT: vpslld $13, %xmm0, %xmm6
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; CHECK-NEXT: vpor %xmm5, %xmm6, %xmm5
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; CHECK-NEXT: vpxor %xmm5, %xmm4, %xmm4
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; CHECK-NEXT: vpsrld $10, %xmm0, %xmm0
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; CHECK-NEXT: vpxor %xmm0, %xmm4, %xmm0
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; CHECK-NEXT: vpaddd %xmm0, %xmm2, %xmm0
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; CHECK-NEXT: vpsrld $17, %xmm0, %xmm4
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; CHECK-NEXT: vpslld $15, %xmm0, %xmm5
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; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm4
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; CHECK-NEXT: vpsrld $19, %xmm0, %xmm5
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; CHECK-NEXT: vpslld $13, %xmm0, %xmm6
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; CHECK-NEXT: vpor %xmm5, %xmm6, %xmm5
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; CHECK-NEXT: vpxor %xmm5, %xmm4, %xmm4
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; CHECK-NEXT: vpsrld $10, %xmm0, %xmm5
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; CHECK-NEXT: vpxor %xmm5, %xmm4, %xmm4
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; CHECK-NEXT: vpblendd {{.*#+}} xmm2 = xmm3[0],xmm2[1],xmm3[2,3]
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; CHECK-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,0,2,3]
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; CHECK-NEXT: vpaddd %xmm4, %xmm2, %xmm2
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; CHECK-NEXT: vpsrld $17, %xmm2, %xmm3
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; CHECK-NEXT: vpslld $15, %xmm2, %xmm4
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; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm3
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; CHECK-NEXT: vpsrld $19, %xmm2, %xmm4
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; CHECK-NEXT: vpslld $13, %xmm2, %xmm5
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; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm4
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; CHECK-NEXT: vpxor %xmm4, %xmm3, %xmm3
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; CHECK-NEXT: vpsrld $10, %xmm2, %xmm2
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; CHECK-NEXT: vpxor %xmm2, %xmm3, %xmm2
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; CHECK-NEXT: vpsrlq $32, %xmm1, %xmm3
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; CHECK-NEXT: vpaddd %xmm2, %xmm3, %xmm1
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; CHECK-NEXT: vpsrld $17, %xmm1, %xmm2
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; CHECK-NEXT: vpslld $15, %xmm1, %xmm4
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; CHECK-NEXT: vpor %xmm2, %xmm4, %xmm2
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; CHECK-NEXT: vpsrld $19, %xmm1, %xmm4
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; CHECK-NEXT: vpslld $13, %xmm1, %xmm5
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; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm4
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; CHECK-NEXT: vpxor %xmm4, %xmm2, %xmm2
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; CHECK-NEXT: vpsrld $10, %xmm1, %xmm4
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; CHECK-NEXT: vpxor %xmm4, %xmm2, %xmm2
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; CHECK-NEXT: vpaddd %xmm2, %xmm3, %xmm2
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; CHECK-NEXT: vpsrld $17, %xmm2, %xmm3
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; CHECK-NEXT: vpslld $15, %xmm2, %xmm4
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; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm3
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; CHECK-NEXT: vpsrld $19, %xmm2, %xmm4
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; CHECK-NEXT: vpslld $13, %xmm2, %xmm5
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; CHECK-NEXT: vpor %xmm4, %xmm5, %xmm4
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; CHECK-NEXT: vpxor %xmm4, %xmm3, %xmm3
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; CHECK-NEXT: vpsrld $10, %xmm2, %xmm2
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; CHECK-NEXT: vpxor %xmm2, %xmm3, %xmm2
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; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0
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; CHECK-NEXT: vpsrld $17, %xmm0, %xmm2
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; CHECK-NEXT: vpslld $15, %xmm0, %xmm3
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; CHECK-NEXT: vpor %xmm2, %xmm3, %xmm2
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; CHECK-NEXT: vpsrld $19, %xmm0, %xmm3
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; CHECK-NEXT: vpslld $13, %xmm0, %xmm4
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; CHECK-NEXT: vpor %xmm3, %xmm4, %xmm3
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; CHECK-NEXT: vpxor %xmm3, %xmm2, %xmm2
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; CHECK-NEXT: vpsrld $10, %xmm0, %xmm3
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; CHECK-NEXT: vpxor %xmm3, %xmm2, %xmm2
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; CHECK-NEXT: vpsllq $32, %xmm1, %xmm3
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; CHECK-NEXT: vpaddd %xmm2, %xmm3, %xmm2
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; CHECK-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
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; CHECK-NEXT: vpunpcklqdq {{.*#+}} ymm0 = ymm1[0],ymm0[0],ymm1[2],ymm0[2]
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; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
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; CHECK-NEXT: vmovdqu %ymm0, 132(%rdi)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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%0 = load i32, ptr null, align 4
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%1 = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %0) #3
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%arrayidx14 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 3
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%2 = load i32, ptr %arrayidx14, align 4
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%3 = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %2) #3
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%4 = insertelement <2 x i32> zeroinitializer, i32 %1, i64 1
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%5 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %4, <2 x i32> %4, <2 x i32> <i32 15, i32 15>)
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%6 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %4, <2 x i32> %4, <2 x i32> <i32 13, i32 13>)
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%7 = xor <2 x i32> %5, %6
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%8 = lshr <2 x i32> %4, zeroinitializer
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%9 = xor <2 x i32> %7, %8
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%10 = insertelement <2 x i32> zeroinitializer, i32 %3, i64 0
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%11 = shufflevector <2 x i32> zeroinitializer, <2 x i32> %10, <2 x i32> <i32 1, i32 2>
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%12 = add <2 x i32> %11, %9
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%13 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %12, <2 x i32> %12, <2 x i32> <i32 15, i32 15>)
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%14 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %12, <2 x i32> %12, <2 x i32> <i32 13, i32 13>)
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%15 = xor <2 x i32> %13, %14
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%16 = lshr <2 x i32> %12, zeroinitializer
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%17 = xor <2 x i32> %15, %16
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%18 = add <2 x i32> %4, %17
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%19 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %18, <2 x i32> %18, <2 x i32> <i32 15, i32 15>)
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%20 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %18, <2 x i32> %18, <2 x i32> <i32 13, i32 13>)
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%21 = xor <2 x i32> %19, %20
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%22 = lshr <2 x i32> %18, <i32 10, i32 10>
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%23 = xor <2 x i32> %21, %22
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%24 = add <2 x i32> %4, %23
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%25 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %24, <2 x i32> %24, <2 x i32> <i32 15, i32 15>)
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%26 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %24, <2 x i32> %24, <2 x i32> <i32 13, i32 13>)
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%27 = xor <2 x i32> %25, %26
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%28 = lshr <2 x i32> %24, <i32 10, i32 10>
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%29 = xor <2 x i32> %27, %28
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%30 = shufflevector <2 x i32> %4, <2 x i32> %12, <2 x i32> <i32 1, i32 2>
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%31 = add <2 x i32> %30, %29
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%32 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %31, <2 x i32> %31, <2 x i32> <i32 15, i32 15>)
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%33 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %31, <2 x i32> %31, <2 x i32> <i32 13, i32 13>)
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%34 = xor <2 x i32> %32, %33
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%35 = lshr <2 x i32> %31, <i32 10, i32 10>
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%36 = xor <2 x i32> %34, %35
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%37 = shufflevector <2 x i32> %12, <2 x i32> zeroinitializer, <2 x i32> <i32 1, i32 2>
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%38 = add <2 x i32> %37, %36
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%arrayidx918 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 33
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store <2 x i32> %38, ptr %arrayidx918, align 4
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%arrayidx1012 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 35
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%39 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %38, <2 x i32> %38, <2 x i32> <i32 15, i32 15>)
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%40 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %38, <2 x i32> %38, <2 x i32> <i32 13, i32 13>)
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%41 = xor <2 x i32> %39, %40
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%42 = lshr <2 x i32> %38, <i32 10, i32 10>
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%43 = xor <2 x i32> %41, %42
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%44 = add <2 x i32> %37, %43
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store <2 x i32> zeroinitializer, ptr %arrayidx1012, align 4
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%arrayidx1106 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 37
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%45 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %44, <2 x i32> %44, <2 x i32> <i32 15, i32 15>)
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%46 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %44, <2 x i32> %44, <2 x i32> <i32 13, i32 13>)
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%47 = xor <2 x i32> %45, %46
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%48 = lshr <2 x i32> %44, <i32 10, i32 10>
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%49 = xor <2 x i32> %47, %48
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%50 = lshr <2 x i32> %24, zeroinitializer
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%51 = add <2 x i32> %50, %49
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store <2 x i32> %51, ptr %arrayidx1106, align 4
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%arrayidx1200 = getelementptr inbounds [64 x i32], ptr %ctx, i64 0, i64 39
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%52 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %51, <2 x i32> %51, <2 x i32> <i32 15, i32 15>)
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%53 = tail call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %51, <2 x i32> %51, <2 x i32> <i32 13, i32 13>)
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%54 = xor <2 x i32> %52, %53
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%55 = lshr <2 x i32> %51, <i32 10, i32 10>
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%56 = xor <2 x i32> %54, %55
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%57 = shufflevector <2 x i32> %38, <2 x i32> zeroinitializer, <2 x i32> <i32 poison, i32 0>
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%58 = insertelement <2 x i32> %57, i32 0, i64 0
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%59 = add <2 x i32> %58, %56
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store <2 x i32> %59, ptr %arrayidx1200, align 4
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ret void
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; uselistorder directives
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uselistorder <2 x i32> %4, { 7, 0, 1, 6, 5, 4, 3, 2 }
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uselistorder <2 x i32> %38, { 6, 5, 4, 3, 2, 1, 0 }
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}
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declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) #2
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; uselistorder directives
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uselistorder ptr @llvm.fshl.v2i32, { 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 }
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attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
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attributes #1 = { nounwind sspstrong memory(argmem: readwrite) uwtable "min-legal-vector-width"="0" "no-trapping-math"="true" "probe-stack"="inline-asm" "stack-protector-buffer-size"="8" "target-cpu"="skylake" "target-features"="+adx,+aes,+avx,+avx2,+bmi,+bmi2,+clflushopt,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sgx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves" }
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attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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attributes #3 = { nounwind memory(none) }
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