f0eb5587ce
This set of instructions was only supported by AMD chips starting in the K6-2 (introduced 1998), and before the "Bulldozer" family (2011). They were never much used, as they were effectively superseded by the more-widely-implemented SSE (first implemented on the AMD side in Athlon XP in 2001). This is being done as a predecessor towards general removal of MMX register usage. Since there is almost no usage of the 3DNow! intrinsics, and no modern hardware even implements them, simple removal seems like the best option. (Clang half originally uploaded in https://reviews.llvm.org/D94213) Works towards issue #41665 and issue #98272.
55 lines
2.5 KiB
LLVM
55 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- -mattr=+sse | FileCheck %s --check-prefix=X86-SSE
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; RUN: llc < %s -mtriple=i686-- -mattr=+avx | FileCheck %s --check-prefix=X86-SSE
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; RUN: llc < %s -mtriple=i686-- -mattr=+sse,+prfchw | FileCheck %s -check-prefix=X86-PRFCHWSSE
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; RUN: llc < %s -mtriple=i686-- -mattr=+prfchw | FileCheck %s -check-prefix=X86-PRFCHWSSE
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; RUN: llc < %s -mtriple=i686-- -mcpu=slm | FileCheck %s -check-prefix=X86-PRFCHWSSE
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; RUN: llc < %s -mtriple=i686-- -mcpu=btver2 | FileCheck %s -check-prefix=X86-PRFCHWSSE
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; RUN: llc < %s -mtriple=i686-- -mcpu=btver2 -mattr=-prfchw | FileCheck %s -check-prefix=X86-SSE
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; RUN: llc < %s -mtriple=i686-- -mattr=+prfchw | FileCheck %s -check-prefix=X86-PRFCHWSSE
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; Rules:
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; sse provides prefetch0/1/2/nta
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; supporting prefetchw implicitly provides prefetcht0/1/2/nta as well, as we need something to fall back to for the non-write hint.
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define void @t(ptr %ptr) nounwind {
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; X86-SSE-LABEL: t:
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; X86-SSE: # %bb.0: # %entry
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; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE-NEXT: prefetcht2 (%eax)
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; X86-SSE-NEXT: prefetcht1 (%eax)
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; X86-SSE-NEXT: prefetcht0 (%eax)
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; X86-SSE-NEXT: prefetchnta (%eax)
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; X86-SSE-NEXT: prefetcht2 (%eax)
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; X86-SSE-NEXT: prefetcht1 (%eax)
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; X86-SSE-NEXT: prefetcht0 (%eax)
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; X86-SSE-NEXT: prefetchnta (%eax)
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; X86-SSE-NEXT: retl
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;
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; X86-PRFCHWSSE-LABEL: t:
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; X86-PRFCHWSSE: # %bb.0: # %entry
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; X86-PRFCHWSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-PRFCHWSSE-NEXT: prefetcht2 (%eax)
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; X86-PRFCHWSSE-NEXT: prefetcht1 (%eax)
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; X86-PRFCHWSSE-NEXT: prefetcht0 (%eax)
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; X86-PRFCHWSSE-NEXT: prefetchnta (%eax)
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; X86-PRFCHWSSE-NEXT: prefetchw (%eax)
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; X86-PRFCHWSSE-NEXT: prefetchw (%eax)
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; X86-PRFCHWSSE-NEXT: prefetchw (%eax)
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; X86-PRFCHWSSE-NEXT: prefetchw (%eax)
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; X86-PRFCHWSSE-NEXT: retl
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entry:
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tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 1, i32 1 )
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tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 2, i32 1 )
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tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 3, i32 1 )
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tail call void @llvm.prefetch( ptr %ptr, i32 0, i32 0, i32 1 )
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tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 1, i32 1 )
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tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 2, i32 1 )
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tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 3, i32 1 )
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tail call void @llvm.prefetch( ptr %ptr, i32 1, i32 0, i32 1 )
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ret void
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}
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declare void @llvm.prefetch(ptr, i32, i32, i32) nounwind
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