551 lines
15 KiB
LLVM
551 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2,-avx | FileCheck %s --check-prefixes=CHECK,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1,-avx | FileCheck %s --check-prefixes=CHECK,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,-avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl,+avx512dq,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
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define i32 @veccond128(<4 x i32> %input) {
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; SSE2-LABEL: veccond128:
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; SSE2: # %bb.0: # %entry
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: movmskps %xmm1, %eax
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; SSE2-NEXT: xorl $15, %eax
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; SSE2-NEXT: je .LBB0_2
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; SSE2-NEXT: # %bb.1: # %if-true-block
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; SSE2-NEXT: xorl %eax, %eax
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; SSE2-NEXT: retq
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; SSE2-NEXT: .LBB0_2: # %endif-block
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; SSE2-NEXT: movl $1, %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: veccond128:
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; SSE41: # %bb.0: # %entry
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; SSE41-NEXT: ptest %xmm0, %xmm0
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; SSE41-NEXT: je .LBB0_2
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; SSE41-NEXT: # %bb.1: # %if-true-block
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; SSE41-NEXT: xorl %eax, %eax
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; SSE41-NEXT: retq
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; SSE41-NEXT: .LBB0_2: # %endif-block
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; SSE41-NEXT: movl $1, %eax
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: veccond128:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vptest %xmm0, %xmm0
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; AVX-NEXT: je .LBB0_2
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; AVX-NEXT: # %bb.1: # %if-true-block
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; AVX-NEXT: xorl %eax, %eax
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; AVX-NEXT: retq
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; AVX-NEXT: .LBB0_2: # %endif-block
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; AVX-NEXT: movl $1, %eax
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; AVX-NEXT: retq
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entry:
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%0 = bitcast <4 x i32> %input to i128
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%1 = icmp ne i128 %0, 0
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br i1 %1, label %if-true-block, label %endif-block
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if-true-block:
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ret i32 0
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endif-block:
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ret i32 1
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}
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define i32 @veccond256(<8 x i32> %input) {
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; SSE2-LABEL: veccond256:
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; SSE2: # %bb.0: # %entry
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; SSE2-NEXT: por %xmm1, %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: movmskps %xmm1, %eax
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; SSE2-NEXT: xorl $15, %eax
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; SSE2-NEXT: je .LBB1_2
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; SSE2-NEXT: # %bb.1: # %if-true-block
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; SSE2-NEXT: xorl %eax, %eax
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; SSE2-NEXT: retq
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; SSE2-NEXT: .LBB1_2: # %endif-block
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; SSE2-NEXT: movl $1, %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: veccond256:
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; SSE41: # %bb.0: # %entry
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; SSE41-NEXT: por %xmm1, %xmm0
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; SSE41-NEXT: ptest %xmm0, %xmm0
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; SSE41-NEXT: je .LBB1_2
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; SSE41-NEXT: # %bb.1: # %if-true-block
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; SSE41-NEXT: xorl %eax, %eax
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; SSE41-NEXT: retq
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; SSE41-NEXT: .LBB1_2: # %endif-block
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; SSE41-NEXT: movl $1, %eax
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: veccond256:
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; AVX: # %bb.0: # %entry
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; AVX-NEXT: vptest %ymm0, %ymm0
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; AVX-NEXT: je .LBB1_2
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; AVX-NEXT: # %bb.1: # %if-true-block
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; AVX-NEXT: xorl %eax, %eax
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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; AVX-NEXT: .LBB1_2: # %endif-block
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; AVX-NEXT: movl $1, %eax
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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entry:
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%0 = bitcast <8 x i32> %input to i256
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%1 = icmp ne i256 %0, 0
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br i1 %1, label %if-true-block, label %endif-block
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if-true-block:
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ret i32 0
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endif-block:
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ret i32 1
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}
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define i32 @veccond512(<16 x i32> %input) {
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; SSE2-LABEL: veccond512:
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; SSE2: # %bb.0: # %entry
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; SSE2-NEXT: por %xmm3, %xmm1
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; SSE2-NEXT: por %xmm2, %xmm0
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; SSE2-NEXT: por %xmm1, %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: movmskps %xmm1, %eax
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; SSE2-NEXT: xorl $15, %eax
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; SSE2-NEXT: je .LBB2_2
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; SSE2-NEXT: # %bb.1: # %if-true-block
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; SSE2-NEXT: xorl %eax, %eax
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; SSE2-NEXT: retq
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; SSE2-NEXT: .LBB2_2: # %endif-block
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; SSE2-NEXT: movl $1, %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: veccond512:
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; SSE41: # %bb.0: # %entry
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; SSE41-NEXT: por %xmm3, %xmm1
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; SSE41-NEXT: por %xmm2, %xmm0
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; SSE41-NEXT: por %xmm1, %xmm0
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; SSE41-NEXT: ptest %xmm0, %xmm0
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; SSE41-NEXT: je .LBB2_2
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; SSE41-NEXT: # %bb.1: # %if-true-block
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; SSE41-NEXT: xorl %eax, %eax
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; SSE41-NEXT: retq
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; SSE41-NEXT: .LBB2_2: # %endif-block
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; SSE41-NEXT: movl $1, %eax
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: veccond512:
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; AVX1: # %bb.0: # %entry
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; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
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; AVX1-NEXT: vptest %ymm0, %ymm0
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; AVX1-NEXT: je .LBB2_2
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; AVX1-NEXT: # %bb.1: # %if-true-block
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; AVX1-NEXT: xorl %eax, %eax
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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; AVX1-NEXT: .LBB2_2: # %endif-block
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; AVX1-NEXT: movl $1, %eax
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: veccond512:
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; AVX512: # %bb.0: # %entry
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; AVX512-NEXT: vptestmd %zmm0, %zmm0, %k0
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; AVX512-NEXT: kortestw %k0, %k0
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; AVX512-NEXT: je .LBB2_2
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; AVX512-NEXT: # %bb.1: # %if-true-block
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; AVX512-NEXT: xorl %eax, %eax
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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; AVX512-NEXT: .LBB2_2: # %endif-block
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; AVX512-NEXT: movl $1, %eax
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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entry:
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%0 = bitcast <16 x i32> %input to i512
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%1 = icmp ne i512 %0, 0
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br i1 %1, label %if-true-block, label %endif-block
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if-true-block:
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ret i32 0
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endif-block:
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ret i32 1
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}
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define i32 @vectest128(<4 x i32> %input) {
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; SSE2-LABEL: vectest128:
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; SSE2: # %bb.0:
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: movmskps %xmm1, %ecx
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; SSE2-NEXT: xorl %eax, %eax
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; SSE2-NEXT: xorl $15, %ecx
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; SSE2-NEXT: setne %al
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: vectest128:
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; SSE41: # %bb.0:
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; SSE41-NEXT: xorl %eax, %eax
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; SSE41-NEXT: ptest %xmm0, %xmm0
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; SSE41-NEXT: setne %al
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: vectest128:
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; AVX: # %bb.0:
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; AVX-NEXT: xorl %eax, %eax
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; AVX-NEXT: vptest %xmm0, %xmm0
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; AVX-NEXT: setne %al
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; AVX-NEXT: retq
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%t0 = bitcast <4 x i32> %input to i128
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%t1 = icmp ne i128 %t0, 0
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%t2 = zext i1 %t1 to i32
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ret i32 %t2
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}
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define i32 @vectest256(<8 x i32> %input) {
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; SSE2-LABEL: vectest256:
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; SSE2: # %bb.0:
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; SSE2-NEXT: por %xmm1, %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: movmskps %xmm1, %ecx
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; SSE2-NEXT: xorl %eax, %eax
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; SSE2-NEXT: xorl $15, %ecx
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; SSE2-NEXT: setne %al
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: vectest256:
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; SSE41: # %bb.0:
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; SSE41-NEXT: por %xmm1, %xmm0
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; SSE41-NEXT: xorl %eax, %eax
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; SSE41-NEXT: ptest %xmm0, %xmm0
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; SSE41-NEXT: setne %al
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: vectest256:
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; AVX: # %bb.0:
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; AVX-NEXT: xorl %eax, %eax
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; AVX-NEXT: vptest %ymm0, %ymm0
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; AVX-NEXT: setne %al
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%t0 = bitcast <8 x i32> %input to i256
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%t1 = icmp ne i256 %t0, 0
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%t2 = zext i1 %t1 to i32
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ret i32 %t2
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}
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define i32 @vectest512(<16 x i32> %input) {
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; SSE2-LABEL: vectest512:
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; SSE2: # %bb.0:
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; SSE2-NEXT: por %xmm3, %xmm1
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; SSE2-NEXT: por %xmm2, %xmm0
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; SSE2-NEXT: por %xmm1, %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: movmskps %xmm1, %ecx
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; SSE2-NEXT: xorl %eax, %eax
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; SSE2-NEXT: xorl $15, %ecx
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; SSE2-NEXT: setne %al
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: vectest512:
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; SSE41: # %bb.0:
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; SSE41-NEXT: por %xmm3, %xmm1
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; SSE41-NEXT: por %xmm2, %xmm0
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; SSE41-NEXT: por %xmm1, %xmm0
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; SSE41-NEXT: xorl %eax, %eax
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; SSE41-NEXT: ptest %xmm0, %xmm0
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; SSE41-NEXT: setne %al
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: vectest512:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
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; AVX1-NEXT: xorl %eax, %eax
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; AVX1-NEXT: vptest %ymm0, %ymm0
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; AVX1-NEXT: setne %al
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: vectest512:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vptestmd %zmm0, %zmm0, %k0
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; AVX512-NEXT: xorl %eax, %eax
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; AVX512-NEXT: kortestw %k0, %k0
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; AVX512-NEXT: setne %al
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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%t0 = bitcast <16 x i32> %input to i512
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%t1 = icmp ne i512 %t0, 0
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%t2 = zext i1 %t1 to i32
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ret i32 %t2
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}
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define i32 @vecsel128(<4 x i32> %input, i32 %a, i32 %b) {
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; SSE2-LABEL: vecsel128:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movl %edi, %eax
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: movmskps %xmm1, %ecx
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; SSE2-NEXT: xorl $15, %ecx
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; SSE2-NEXT: cmovel %esi, %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: vecsel128:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movl %edi, %eax
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; SSE41-NEXT: ptest %xmm0, %xmm0
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; SSE41-NEXT: cmovel %esi, %eax
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: vecsel128:
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; AVX: # %bb.0:
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; AVX-NEXT: movl %edi, %eax
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; AVX-NEXT: vptest %xmm0, %xmm0
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; AVX-NEXT: cmovel %esi, %eax
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; AVX-NEXT: retq
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%t0 = bitcast <4 x i32> %input to i128
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%t1 = icmp ne i128 %t0, 0
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%t2 = select i1 %t1, i32 %a, i32 %b
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ret i32 %t2
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}
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define i32 @vecsel256(<8 x i32> %input, i32 %a, i32 %b) {
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; SSE2-LABEL: vecsel256:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movl %edi, %eax
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; SSE2-NEXT: por %xmm1, %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: movmskps %xmm1, %ecx
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; SSE2-NEXT: xorl $15, %ecx
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; SSE2-NEXT: cmovel %esi, %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: vecsel256:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movl %edi, %eax
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; SSE41-NEXT: por %xmm1, %xmm0
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; SSE41-NEXT: ptest %xmm0, %xmm0
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; SSE41-NEXT: cmovel %esi, %eax
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: vecsel256:
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; AVX: # %bb.0:
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; AVX-NEXT: movl %edi, %eax
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; AVX-NEXT: vptest %ymm0, %ymm0
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; AVX-NEXT: cmovel %esi, %eax
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; AVX-NEXT: vzeroupper
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; AVX-NEXT: retq
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%t0 = bitcast <8 x i32> %input to i256
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%t1 = icmp ne i256 %t0, 0
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%t2 = select i1 %t1, i32 %a, i32 %b
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ret i32 %t2
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}
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define i32 @vecsel512(<16 x i32> %input, i32 %a, i32 %b) {
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; SSE2-LABEL: vecsel512:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movl %edi, %eax
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; SSE2-NEXT: por %xmm3, %xmm1
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; SSE2-NEXT: por %xmm2, %xmm0
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; SSE2-NEXT: por %xmm1, %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: movmskps %xmm1, %ecx
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; SSE2-NEXT: xorl $15, %ecx
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; SSE2-NEXT: cmovel %esi, %eax
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: vecsel512:
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; SSE41: # %bb.0:
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; SSE41-NEXT: movl %edi, %eax
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; SSE41-NEXT: por %xmm3, %xmm1
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; SSE41-NEXT: por %xmm2, %xmm0
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; SSE41-NEXT: por %xmm1, %xmm0
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; SSE41-NEXT: ptest %xmm0, %xmm0
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; SSE41-NEXT: cmovel %esi, %eax
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; SSE41-NEXT: retq
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;
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; AVX1-LABEL: vecsel512:
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; AVX1: # %bb.0:
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; AVX1-NEXT: movl %edi, %eax
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; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
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; AVX1-NEXT: vptest %ymm0, %ymm0
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; AVX1-NEXT: cmovel %esi, %eax
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; AVX1-NEXT: vzeroupper
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: vecsel512:
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; AVX512: # %bb.0:
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; AVX512-NEXT: movl %edi, %eax
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; AVX512-NEXT: vptestmd %zmm0, %zmm0, %k0
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; AVX512-NEXT: kortestw %k0, %k0
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; AVX512-NEXT: cmovel %esi, %eax
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; AVX512-NEXT: vzeroupper
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; AVX512-NEXT: retq
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%t0 = bitcast <16 x i32> %input to i512
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%t1 = icmp ne i512 %t0, 0
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%t2 = select i1 %t1, i32 %a, i32 %b
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ret i32 %t2
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}
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define i1 @vecmp_load64x2(ptr %p0) {
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; CHECK-LABEL: vecmp_load64x2:
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|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: movq (%rdi), %rax
|
|
; CHECK-NEXT: orq 8(%rdi), %rax
|
|
; CHECK-NEXT: sete %al
|
|
; CHECK-NEXT: retq
|
|
%p1 = getelementptr i8, ptr %p0, i64 8
|
|
%i0 = load i64, ptr %p0, align 1
|
|
%i1 = load i64, ptr %p1, align 1
|
|
%or = or i64 %i0, %i1
|
|
%ne = icmp ne i64 %or, 0
|
|
%zx = zext i1 %ne to i32
|
|
%eq = icmp eq i32 %zx, 0
|
|
ret i1 %eq
|
|
}
|
|
|
|
define i1 @vecmp_load64x4(ptr %p0) {
|
|
; CHECK-LABEL: vecmp_load64x4:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: movq (%rdi), %rax
|
|
; CHECK-NEXT: movq 8(%rdi), %rcx
|
|
; CHECK-NEXT: orq 16(%rdi), %rax
|
|
; CHECK-NEXT: orq 24(%rdi), %rcx
|
|
; CHECK-NEXT: orq %rax, %rcx
|
|
; CHECK-NEXT: sete %al
|
|
; CHECK-NEXT: retq
|
|
%p1 = getelementptr i8, ptr %p0, i64 8
|
|
%p2 = getelementptr i8, ptr %p0, i64 16
|
|
%p3 = getelementptr i8, ptr %p0, i64 24
|
|
%i0 = load i64, ptr %p0, align 1
|
|
%i1 = load i64, ptr %p1, align 1
|
|
%i2 = load i64, ptr %p2, align 1
|
|
%i3 = load i64, ptr %p3, align 1
|
|
%or02 = or i64 %i0, %i2
|
|
%or13 = or i64 %i1, %i3
|
|
%or = or i64 %or02, %or13
|
|
%ne = icmp ne i64 %or, 0
|
|
%zx = zext i1 %ne to i32
|
|
%eq = icmp eq i32 %zx, 0
|
|
ret i1 %eq
|
|
}
|
|
|
|
define i1 @vecmp_load128x2(ptr %p0) {
|
|
; CHECK-LABEL: vecmp_load128x2:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: movq (%rdi), %rax
|
|
; CHECK-NEXT: movq 8(%rdi), %rcx
|
|
; CHECK-NEXT: orq 24(%rdi), %rcx
|
|
; CHECK-NEXT: orq 16(%rdi), %rax
|
|
; CHECK-NEXT: orq %rcx, %rax
|
|
; CHECK-NEXT: sete %al
|
|
; CHECK-NEXT: retq
|
|
%p1 = getelementptr i8, ptr %p0, i64 16
|
|
%i0 = load i128, ptr %p0, align 1
|
|
%i1 = load i128, ptr %p1, align 1
|
|
%or = or i128 %i0, %i1
|
|
%ne = icmp ne i128 %or, 0
|
|
%zx = zext i1 %ne to i32
|
|
%eq = icmp eq i32 %zx, 0
|
|
ret i1 %eq
|
|
}
|
|
|
|
define i1 @vecmp_load128x4(ptr %p0) {
|
|
; CHECK-LABEL: vecmp_load128x4:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: movq (%rdi), %rax
|
|
; CHECK-NEXT: movq 8(%rdi), %rcx
|
|
; CHECK-NEXT: movq 24(%rdi), %rdx
|
|
; CHECK-NEXT: movq 16(%rdi), %rsi
|
|
; CHECK-NEXT: orq 32(%rdi), %rax
|
|
; CHECK-NEXT: orq 40(%rdi), %rcx
|
|
; CHECK-NEXT: orq 48(%rdi), %rsi
|
|
; CHECK-NEXT: orq %rax, %rsi
|
|
; CHECK-NEXT: orq 56(%rdi), %rdx
|
|
; CHECK-NEXT: orq %rcx, %rdx
|
|
; CHECK-NEXT: orq %rsi, %rdx
|
|
; CHECK-NEXT: sete %al
|
|
; CHECK-NEXT: retq
|
|
%p1 = getelementptr i8, ptr %p0, i64 16
|
|
%p2 = getelementptr i8, ptr %p0, i64 32
|
|
%p3 = getelementptr i8, ptr %p0, i64 48
|
|
%i0 = load i128, ptr %p0, align 1
|
|
%i1 = load i128, ptr %p1, align 1
|
|
%i2 = load i128, ptr %p2, align 1
|
|
%i3 = load i128, ptr %p3, align 1
|
|
%or02 = or i128 %i0, %i2
|
|
%or13 = or i128 %i1, %i3
|
|
%or = or i128 %or02, %or13
|
|
%ne = icmp ne i128 %or, 0
|
|
%zx = zext i1 %ne to i32
|
|
%eq = icmp eq i32 %zx, 0
|
|
ret i1 %eq
|
|
}
|
|
|
|
; PR144861
|
|
define i1 @vecmp_load256x2(ptr %p0) {
|
|
; CHECK-LABEL: vecmp_load256x2:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: movq 24(%rdi), %rax
|
|
; CHECK-NEXT: movq (%rdi), %rcx
|
|
; CHECK-NEXT: movq 8(%rdi), %rdx
|
|
; CHECK-NEXT: movq 16(%rdi), %rsi
|
|
; CHECK-NEXT: orq 48(%rdi), %rsi
|
|
; CHECK-NEXT: orq 32(%rdi), %rcx
|
|
; CHECK-NEXT: orq %rsi, %rcx
|
|
; CHECK-NEXT: orq 56(%rdi), %rax
|
|
; CHECK-NEXT: orq 40(%rdi), %rdx
|
|
; CHECK-NEXT: orq %rax, %rdx
|
|
; CHECK-NEXT: orq %rcx, %rdx
|
|
; CHECK-NEXT: sete %al
|
|
; CHECK-NEXT: retq
|
|
%p1 = getelementptr i8, ptr %p0, i64 32
|
|
%i0 = load i256, ptr %p0, align 1
|
|
%i1 = load i256, ptr %p1, align 1
|
|
%or = or i256 %i0, %i1
|
|
%ne = icmp ne i256 %or, 0
|
|
%zx = zext i1 %ne to i32
|
|
%eq = icmp eq i32 %zx, 0
|
|
ret i1 %eq
|
|
}
|
|
|
|
define i1 @vecmp_load512x2(ptr %p0) {
|
|
; CHECK-LABEL: vecmp_load512x2:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: movq 24(%rdi), %rax
|
|
; CHECK-NEXT: movq 56(%rdi), %rdx
|
|
; CHECK-NEXT: movq 40(%rdi), %rsi
|
|
; CHECK-NEXT: movq 16(%rdi), %rcx
|
|
; CHECK-NEXT: movq 48(%rdi), %r8
|
|
; CHECK-NEXT: movq (%rdi), %r9
|
|
; CHECK-NEXT: movq 8(%rdi), %r10
|
|
; CHECK-NEXT: movq 32(%rdi), %r11
|
|
; CHECK-NEXT: orq 96(%rdi), %r11
|
|
; CHECK-NEXT: orq 64(%rdi), %r9
|
|
; CHECK-NEXT: orq %r11, %r9
|
|
; CHECK-NEXT: orq 112(%rdi), %r8
|
|
; CHECK-NEXT: orq 80(%rdi), %rcx
|
|
; CHECK-NEXT: orq %r8, %rcx
|
|
; CHECK-NEXT: orq %r9, %rcx
|
|
; CHECK-NEXT: orq 104(%rdi), %rsi
|
|
; CHECK-NEXT: orq 72(%rdi), %r10
|
|
; CHECK-NEXT: orq %rsi, %r10
|
|
; CHECK-NEXT: orq 120(%rdi), %rdx
|
|
; CHECK-NEXT: orq 88(%rdi), %rax
|
|
; CHECK-NEXT: orq %rdx, %rax
|
|
; CHECK-NEXT: orq %r10, %rax
|
|
; CHECK-NEXT: orq %rcx, %rax
|
|
; CHECK-NEXT: sete %al
|
|
; CHECK-NEXT: retq
|
|
%p1 = getelementptr i8, ptr %p0, i64 64
|
|
%i0 = load i512, ptr %p0, align 1
|
|
%i1 = load i512, ptr %p1, align 1
|
|
%or = or i512 %i0, %i1
|
|
%ne = icmp ne i512 %or, 0
|
|
%zx = zext i1 %ne to i32
|
|
%eq = icmp eq i32 %zx, 0
|
|
ret i1 %eq
|
|
}
|