b7e4fba6e5
After #98505, the textual IR keyword `x86_mmx` was temporarily made to parse as `<1 x i64>`, so as not to require a lot of test update noise. This completes the removal of the type, by removing the`x86_mmx` keyword from the IR parser, and making the (now no-op) test updates via `sed -i 's/\bx86_mmx\b/<1 x i64>/g' $(git grep -l x86_mmx llvm/test/)`. Resulting bitcasts from <1 x i64> to itself were then manually deleted. Changes to llvm/test/Bitcode/compatibility-$VERSION.ll were reverted, as they're intended to be equivalent to the .bc file, if parsed by old LLVM, so shouldn't be updated. A few tests were removed, as they're no longer testing anything, in the following files: - llvm/test/Transforms/GlobalOpt/x86_mmx_load.ll - llvm/test/Transforms/InstCombine/cast.ll - llvm/test/Transforms/InstSimplify/ConstProp/gep-zeroinit-vector.ll Works towards issue #98272.
132 lines
4.1 KiB
LLVM
132 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X64
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define i32 @test0(ptr %v4) nounwind {
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; X86-LABEL: test0:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: pshufw $238, (%eax), %mm0 # mm0 = mem[2,3,2,3]
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; X86-NEXT: movd %mm0, %eax
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; X86-NEXT: addl $32, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test0:
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; X64: # %bb.0: # %entry
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; X64-NEXT: pshufw $238, (%rdi), %mm0 # mm0 = mem[2,3,2,3]
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; X64-NEXT: movd %mm0, %eax
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; X64-NEXT: addl $32, %eax
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; X64-NEXT: retq
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entry:
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%v5 = load <1 x i64>, ptr %v4, align 8
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%v12 = bitcast <1 x i64> %v5 to <4 x i16>
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%v13 = bitcast <4 x i16> %v12 to <1 x i64>
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%v14 = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> %v13, i8 -18)
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%v15 = bitcast <1 x i64> %v14 to <4 x i16>
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%v16 = bitcast <4 x i16> %v15 to <1 x i64>
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%v17 = extractelement <1 x i64> %v16, i32 0
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%v18 = bitcast i64 %v17 to <2 x i32>
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%v19 = extractelement <2 x i32> %v18, i32 0
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%v20 = add i32 %v19, 32
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ret i32 %v20
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}
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define i32 @test1(ptr nocapture readonly %ptr) nounwind {
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; X86-LABEL: test1:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movd (%eax), %mm0
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; X86-NEXT: pshufw $232, %mm0, %mm0 # mm0 = mm0[0,2,2,3]
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; X86-NEXT: movd %mm0, %eax
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; X86-NEXT: emms
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; X86-NEXT: retl
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;
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; X64-LABEL: test1:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movd (%rdi), %mm0
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; X64-NEXT: pshufw $232, %mm0, %mm0 # mm0 = mm0[0,2,2,3]
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; X64-NEXT: movd %mm0, %eax
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; X64-NEXT: emms
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; X64-NEXT: retq
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entry:
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%0 = load i32, ptr %ptr, align 4
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%1 = insertelement <2 x i32> undef, i32 %0, i32 0
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%2 = insertelement <2 x i32> %1, i32 0, i32 1
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%3 = bitcast <2 x i32> %2 to <1 x i64>
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%4 = bitcast <1 x i64> %3 to i64
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%5 = bitcast i64 %4 to <4 x i16>
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%6 = bitcast <4 x i16> %5 to <1 x i64>
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%7 = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> %6, i8 -24)
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%8 = bitcast <1 x i64> %7 to <4 x i16>
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%9 = bitcast <4 x i16> %8 to <1 x i64>
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%10 = extractelement <1 x i64> %9, i32 0
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%11 = bitcast i64 %10 to <2 x i32>
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%12 = extractelement <2 x i32> %11, i32 0
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tail call void @llvm.x86.mmx.emms()
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ret i32 %12
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}
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define i32 @test2(ptr nocapture readonly %ptr) nounwind {
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; X86-LABEL: test2:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: pshufw $232, (%eax), %mm0 # mm0 = mem[0,2,2,3]
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; X86-NEXT: movd %mm0, %eax
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; X86-NEXT: emms
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; X86-NEXT: retl
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;
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; X64-LABEL: test2:
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; X64: # %bb.0: # %entry
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; X64-NEXT: pshufw $232, (%rdi), %mm0 # mm0 = mem[0,2,2,3]
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; X64-NEXT: movd %mm0, %eax
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; X64-NEXT: emms
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; X64-NEXT: retq
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entry:
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%0 = load <1 x i64>, ptr %ptr, align 8
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%1 = tail call <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64> %0, i8 -24)
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%2 = bitcast <1 x i64> %1 to <4 x i16>
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%3 = bitcast <4 x i16> %2 to <1 x i64>
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%4 = extractelement <1 x i64> %3, i32 0
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%5 = bitcast i64 %4 to <2 x i32>
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%6 = extractelement <2 x i32> %5, i32 0
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tail call void @llvm.x86.mmx.emms()
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ret i32 %6
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}
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define i32 @test3(<1 x i64> %a) nounwind {
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; X86-LABEL: test3:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test3:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: # kill: def $eax killed $eax killed $rax
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; X64-NEXT: retq
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%tmp0 = bitcast <1 x i64> %a to <2 x i32>
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%tmp1 = extractelement <2 x i32> %tmp0, i32 0
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ret i32 %tmp1
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}
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; Verify we don't muck with extractelts from the upper lane.
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define i32 @test4(<1 x i64> %a) nounwind {
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; X86-LABEL: test4:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test4:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %xmm0
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; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
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; X64-NEXT: movd %xmm0, %eax
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; X64-NEXT: retq
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%tmp0 = bitcast <1 x i64> %a to <2 x i32>
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%tmp1 = extractelement <2 x i32> %tmp0, i32 1
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ret i32 %tmp1
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}
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declare <1 x i64> @llvm.x86.sse.pshuf.w(<1 x i64>, i8)
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declare void @llvm.x86.mmx.emms()
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