b7e4fba6e5
After #98505, the textual IR keyword `x86_mmx` was temporarily made to parse as `<1 x i64>`, so as not to require a lot of test update noise. This completes the removal of the type, by removing the`x86_mmx` keyword from the IR parser, and making the (now no-op) test updates via `sed -i 's/\bx86_mmx\b/<1 x i64>/g' $(git grep -l x86_mmx llvm/test/)`. Resulting bitcasts from <1 x i64> to itself were then manually deleted. Changes to llvm/test/Bitcode/compatibility-$VERSION.ll were reverted, as they're intended to be equivalent to the .bc file, if parsed by old LLVM, so shouldn't be updated. A few tests were removed, as they're no longer testing anything, in the following files: - llvm/test/Transforms/GlobalOpt/x86_mmx_load.ll - llvm/test/Transforms/InstCombine/cast.ll - llvm/test/Transforms/InstSimplify/ConstProp/gep-zeroinit-vector.ll Works towards issue #98272.
80 lines
2.1 KiB
LLVM
80 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-darwin -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse4.1 | FileCheck %s --check-prefix=X64
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; This is not an MMX operation; promoted to xmm.
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define <1 x i64> @t0(i32 %A) nounwind {
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; X86-LABEL: t0:
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; X86: ## %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: xorl %eax, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: t0:
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; X64: ## %bb.0:
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; X64-NEXT: movd %edi, %xmm0
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; X64-NEXT: psllq $32, %xmm0
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; X64-NEXT: movq %xmm0, %rax
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; X64-NEXT: retq
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%tmp3 = insertelement <2 x i32> < i32 0, i32 undef >, i32 %A, i32 1
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%tmp4 = bitcast <2 x i32> %tmp3 to <1 x i64>
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ret <1 x i64> %tmp4
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}
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define <8 x i8> @t1(i8 zeroext %x) nounwind {
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; X86-LABEL: t1:
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; X86: ## %bb.0:
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; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-NEXT: retl
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;
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; X64-LABEL: t1:
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; X64: ## %bb.0:
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; X64-NEXT: movd %edi, %xmm0
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; X64-NEXT: retq
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%r = insertelement <8 x i8> undef, i8 %x, i32 0
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ret <8 x i8> %r
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}
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; PR2574
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define <2 x float> @t2(<2 x float> %a0) {
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; X86-LABEL: t2:
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; X86: ## %bb.0:
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; X86-NEXT: xorps %xmm0, %xmm0
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; X86-NEXT: retl
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;
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; X64-LABEL: t2:
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; X64: ## %bb.0:
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; X64-NEXT: xorps %xmm0, %xmm0
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; X64-NEXT: retq
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%v1 = insertelement <2 x float> %a0, float 0.000000e+00, i32 0
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%v2 = insertelement <2 x float> %v1, float 0.000000e+00, i32 1
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ret <2 x float> %v2
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}
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@g0 = external global i16
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@g1 = external global <4 x i16>
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; PR2562
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define void @t3() {
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; X86-LABEL: t3:
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; X86: ## %bb.0:
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; X86-NEXT: movl L_g0$non_lazy_ptr, %eax
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; X86-NEXT: movzwl (%eax), %eax
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; X86-NEXT: movl L_g1$non_lazy_ptr, %ecx
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; X86-NEXT: movw %ax, (%ecx)
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; X86-NEXT: retl
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;
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; X64-LABEL: t3:
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; X64: ## %bb.0:
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; X64-NEXT: movq _g0@GOTPCREL(%rip), %rax
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; X64-NEXT: movzwl (%rax), %eax
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; X64-NEXT: movq _g1@GOTPCREL(%rip), %rcx
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; X64-NEXT: movw %ax, (%rcx)
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; X64-NEXT: retq
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load i16, ptr @g0
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load <4 x i16>, ptr @g1
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insertelement <4 x i16> %2, i16 %1, i32 0
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store <4 x i16> %3, ptr @g1
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ret void
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}
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