16facf1ca6
Single-element vectors are legalized by splitting, so the the memory operations would also get scalarized. While we do have some support to reconstruct scalarized loads, we clearly don't catch everything. The comment for the affected AArch64 store suggests that having two stores was the desired outcome in the first place. This was showing as a source of *many* regressions with more aggressive ZERO_EXTEND_VECTOR_INREG recognition.
39 lines
1.4 KiB
LLVM
39 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-linux -mattr=+sse4.2 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse4.2 | FileCheck %s --check-prefix=X64
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; PR4891
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; Both loads should happen before either store.
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define void @short2_int_swap(ptr nocapture %b, ptr nocapture %c) nounwind {
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; X86-LABEL: short2_int_swap:
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; X86: # %bb.0: # %entry
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl (%ecx), %edx
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; X86-NEXT: movl (%eax), %esi
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; X86-NEXT: movl %esi, (%ecx)
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; X86-NEXT: movl %edx, (%eax)
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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;
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; X64-LABEL: short2_int_swap:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movl (%rdi), %eax
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; X64-NEXT: movl (%rsi), %ecx
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; X64-NEXT: movl %ecx, (%rdi)
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; X64-NEXT: movl %eax, (%rsi)
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; X64-NEXT: retq
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entry:
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%0 = load <2 x i16>, ptr %b, align 2 ; <<2 x i16>> [#uses=1]
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%1 = load i32, ptr %c, align 4 ; <i32> [#uses=1]
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%tmp1 = bitcast i32 %1 to <2 x i16> ; <<2 x i16>> [#uses=1]
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store <2 x i16> %tmp1, ptr %b, align 2
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%tmp5 = bitcast <2 x i16> %0 to <1 x i32> ; <<1 x i32>> [#uses=1]
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%tmp3 = extractelement <1 x i32> %tmp5, i32 0 ; <i32> [#uses=1]
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store i32 %tmp3, ptr %c, align 4
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ret void
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}
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